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INTRODUCTION
The i960 Jx processor has approximately 5 to 10 times faster interrupt servicing than the i960 Kx
processor. This is accomplished through a number of features:
•
a hardware priority resolver removes the need to access the external interrupt table to resolve
interrupts
•
caching of dedicated-mode interrupt vectors in the internal data RAM
•
reserving frames in the local register cache for high-priority interrupts
•
the ability to lock the code of interrupt service routines in the instruction-cache reduces the
fetch latency for starting up these routines
CHAPTER 11, INTERRUPTS
1.1.6
Timer Support
The i960 Jx processor provides two identical 32-bit timers. Access to the timers is through
memory-mapped registers. The timers have a single-shot mode and auto-reload capabilities for
continuous operation. Each timer has an independent interrupt request to the i960 Jx processor
interrupt controller. See
CHAPTER 10, TIMERS
1.1.7
Memory-Mapped Control Registers (MMR)
Control registers in the i960 Jx processor are memory-mapped to allow for visibility to application
software. This includes registers for memory configuration, internally cached PRCB data,
breakpoint registers, and interrupt control. These registers are mapped to the architecturally
reserved address space range of FF00 0000H to FFFF FFFFH. The processor ensures that accesses
to the MMRs generate no external bus cycles.
Section 3.3, MEMORY-MAPPED CONTROL REGISTERS (pg. 3-6)
detail.
1.1.8
External Bus
The 32-bit multiplexed external bus connects the i960 Jx processor to memory and I/O. This high
bandwidth bus provides burst transfer capability allowing up to four successive 32-bit data word
transfers at a maximum rate of one word every clock cycle. In addition to the bus signals, the i960
Jx processor provides signals to allow external bus masters. Lastly, the processor provides
variable bus-width support (8-, 16-, and 32-bit).
1-6
discusses this in more detail.
for a complete description.
discusses this in more
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