Source Synchronous - Data; Signal Trace Length Match Mapping - Intel Pentium M Processor Design Manual

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Intel Pentium M Processor and Intel
System Bus Routing Guidelines
since the dielectric thickness, line width, and velocity of the signals may be uniform across a single
layer of the stack-up. A relationship of dielectric thickness, line width, and velocity between layers
is not ensured.
The source synchronous signals should be routed as a strip-line on an internal layer with complete
reference to ground planes both above and below the signal layer. Routing with references to split
planes or power planes other than ground is not allowed. For the recommended stack-up example,
see Figure
Skew minimization requires pad-to-pad trace length matching of the Intel Pentium M processor
system bus source synchronous signals that belong to the same group including the strobe signals
of that group.
5.1.5.2 Source Synchronous – Data
Robust operation of the 400 MHz, source synchronous data signals require tight skew control. For
this reason, these signals are split into matched groups as outlined in
within the same group must be kept on the same layer of motherboard routing and should be routed
to the same pad-to-pad length within ±100 mils of the associated strobes. The two complementary
strobe signals associated with each group should be length-matched to each other within ± 25 mils
and tuned within ± 25 mils to the average length of the data signals of their associated group.
Group-to-group should be length-matched to each other within ±100 mils. This may optimize
setup/hold time margin.
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Table 18. Intel Pentium

Signal Trace Length Match Mapping

CPU Signal Name
D[15:0]#, DINV0#
D[31:16]#, DINV1#
D[47:32]#, DINV2#
D[63:48]#, DINV3#
1. Strobes of the same group should be trace length-matched to each other within ±25 mils and to the
average length of their associated Data signal group.
2. Group-to-group should be length-matched to each other within ±100 mils.
Table 19
400 MHz, high frequency operation of the data signals, they must maintain a 1:3 spacing and
should be limited to a pad-to-pad trace length minimum of 3.0 inches and maximum of 7.5 inches.
The data strobes must also maintain a 1:3 spacing. In this case, the Intel
DSTBN[3:0]# and DSTBP[3:0]# strobe signals must be routed to the Intel
HDSTBN[3:0]# and HDSTBP[3:0]# strobe signals with 1:3 spacing from all signals.
62
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E7501 Chipset Platform
6.
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M Processor System Bus Data Source Synchronous
Signal Matching
± 100 mils
lists the source synchronous data signal general routing requirements. Due to the
Strobes Associated with the Group
DSTBP0#, DSTBN0#
DSTBP1#, DSTBN1#
DSTBP2#, DSTBN2#
DSTBP3#, DSTBN3#
Table 18. All the signals
Strobe Matching
± 25 mils
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Pentium M processor's
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E7501 MCH's
Design Guide