HP 70427A User Manual page 510

Block Diagram
Controller, I/O Interface and Power Supply Assembly A6
6 dB/octave, and the noise becomes equivalent to a unity gain inverting
buffer. The typical noise of an OP-27 in this configuration is 4.5 nV/Hz.
The regulator's output voltage is controlled by enhancement mode power
MOS FETs. The P-Channel MOS FETs used in the negative supplies will
dissipate up to 74 W, with V 50 V, and I = 18 A. The ON resistance is
dss d
0.14Ω at 9.3 A. The N-Channel MOS FETs used in the positive supplies will
dissipate up to 125 W, with V = 50 V, and I = 35 A. The ON resistance is
dss d
0.028Ω at 29 A. The gate threshold voltages are each 4 V .
max
The advantage of a power MOS FET is the low drive current requirement,
and as little as 0.5 V to 0.8 V voltage drop across the drain and source. The
gate leakage current is 250 μA maximum. The disadvantage is that its gate
capacitance is 3000 pF, and the drive voltage must be at least 4 volts greater
than the source for current to flow.
The regulator op-amps are unstable driving the capacitive gate of the MOS
FETs directly. Amplifier stability is insured by driving the MOS FET
through the 100Ω gate resistors. This insures the op-amp stability, but an
additional pole is added to the regulator's loop response at 530 kHz. In order
to maintain loop stability when the op-amp gain cross-over occurs, this pole
must be compensated for.
The phase shift produced by the pole formed by the gate resistors and the
gate of the MOS FET is compensated for by adding a pole/zero pair around
the regulator op-amps. The pole is at DC, which produces an integrator
response until the zero at 457 kHz. This zero also sets the loop gain to –6 dB
to prevent loop peaking due to the 530 kHz pole.
The regulator op-amp power is supplied by the un-regulated ±15 V supplies.
This provides ±16.5 V under normal load conditions, and never drops below
±15.5 V at maximum current. This provides ample voltage to supply the
op-amps which drive the MOS FET pass transistors on the ±10 V and ±5 V
supplies directly. The regulator op-amp output on the ±15 V supplies must
be level shifted to provide the required gate threshold voltage.
Level shifting is accomplished by rectifying the peak voltage off the 15 V
winding of transformer T107, to produce ±26 V. +26 V is connected to the
pass transistor (Q105) in the +15 V regulator through a 3.9 mA constant
current diode (CR103). The 3.9 mA drawn through R120 (2.61 k) produces a
constant level shift of 10.2 V. The 10 μF capacitor (C119) provides an AC
short across R120 at frequencies above 10 kHz.
Similarly, the –26 V is connected to the pass transistor (Q109) in the –15 V
regulator through a 3.9 mA constant current diode (CR126). The 3.9 mA
drawn through R134 (2.61 k) produces a constant level shift of –10.2 V. The
10 μF capacitor (C46) provides an AC short across R134 at frequencies
above 10 kHz.
The over-current protection on each of the six regulated supplies is designed
to shut off the affected supplies without causing damage to the supply or
HP 70427A/HP 70428A User's Guide 13-75