HP 70427A User Manual page 464

kHz bandwidth modes. This offset level is sufficient to ramp the integrator
over its entire output range in less than 200 ms. The integrator response time
in the 4 kHz bandwidth is much slower. It is necessary to increase the
integrator offset to ±2.7 V to insure the entire output range will be swept in
less than 200 ms.
The maximum integrator sweep offset which can be tolerated by the PLL
must be sufficiently less than the phase detector output phase slope that:
1. The phase detector output can override the sweep-to-lock offset and
acquire phase lock.
2. The PLL must maintain phase lock through the phase transients
generated by the sweep circuit turning off.
600 MHz STW Oscillator
The 600 MHz STWO is a transverse wave resonator oscillator designed for
low noise performance and wide tuning range. The tuning sensitivity is
typically 10 kHz/V at 600 MHz or approximately 20 ppm/V. It is designed to
oscillate at 600 MHz, +160 kHz @ –9 V tune line voltage and –100 kHz at
+12 V tune line voltage. The oscillator is offset +21.9 kHz with 0 V on the
tune line to compensate for the temperature drift of the transverse wave
resonator. The exact frequency of oscillation is not important for phase noise
measurements, but the STWO must be able to acquire and maintain
phase-lock under all environmental conditions with the internal 100 MHz
VCXO, tunable over a ±10 ppm range, which is ±6 kHz at 600 MHz.
Table 13-8 Phase Noise Performance
Offset Frequency
10 Hz
100 Hz
1 KHz
10 kHz
>100 kHz
The phase noise performance is achieved by using very high-Q STW
resonators with very small burst noise, a circuit topology that is inherently
low noise, an active device which maintains good residual noise
performance as an amplifier, even while limiting, and by paying special
attention to oscillator bias supply voltages. The capacitance multiplier
regulator on the oscillator's collector supply greatly reduces the power
supply noise which would be converted to phase noise in the oscillator. The
Typical Noise Oscillator Performance Requirements
Performance
Specified
–70 dBc –28 dBc
–100 dBc –78 dBc
–130 dBc –128 dBc
–160 dBc –158 dBc
–175 dBc –170 dBc
HP 70427A/HP 70428A User's Guide 13-29
Block Diagram
600 MHz Reference Loop (A7A2)
Typical
–25 dBc
–75 dBc
–125 dBc
–155 dBc
–167 dBc