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Block Diagram
YIG-Tuned-Filter (YTF) and GaAs FET Amplifier Driver Assembly
The disadvantage of drain bias control is in level accuracy and level
switching speed. The level accuracy is about ±3 db. The switching speed is
slow because the output level is dependent on drain voltage driver transistor
junction temperature and MMIC device temperature. In ALC ON mode,
time is taken to allow the thermal transients to decay, while constantly
re-adjusting the output level. The switching time from +20 dBm to 0 dBm is
as much as 5 seconds.
The output level control DAC (U7) also controls the drain bias control mode.
In drain bias control mode, the second gate control switch (U26) is opened,
which allows the second gates of the MMICs to float to their normal internal
bias levels.
GaAs FET Amplifier Drain Bias Supply
The drain bias supply regulates and controls the bias voltage for the six
MMIC GaAs FET amplifiers. Its output voltage range is 0.0 V to +7.0 V.
Each of the MMIC amplifier stages has an output designed for its nominal
current requirement, with individual current monitoring capability. Stages 1
to 4 are set to 100 mA of bias current. Stages 5 and 6 are set to 150 mA.
The drain voltage shutdown circuit protects the MMICs against
over-currenting due to loss of 1st gate bias.
The drain bias supply has two modes of operation: second gate control mode
which requires a fixed 7.0 V output, and drain bias control which has a
variable voltage output of 0.0 V to +7.0 V.
The reference for the fixed +7.0 V output operation is derived from the +10.0
volt reference. A resistive voltage divider consisting of R116 and R117 is
buffered by the emitter follower transistor Q22 to produce a +7.8 V
reference voltage.
The variable voltage output reference is supplied by amplifying the output
level control DAC (U7) by a gain of – 0.75 in op-amp U29. This produces a
0 V to 7.5 V reference.
A quad-FET switch (U28) is used to switch between modes. The FET switch
output is then filtered by an 0.18 Hz adaptive noise filter. The noise filter
reduces the 100 nV/Hz reference noise to less than 3 nV/Hz at 6 Hz. The
adaptive filter is buffered by a voltage follower (U27). The voltage follower
input noise sets the noise at 3 nV/Hz beyond 60 Hz.
The adaptive noise filter is switched out during level setting. The switching
is done by shunting the 100 kΩ filter input resistor with 50Ω, which
increases the cutoff frequency to 215 Hz.
The drain voltage shutdown circuit monitors the –10 V supply used to bias
the 1st gate in the MMICs. Loss of the gate bias will force the MMICs to
operate at I dss which may exceed their absolute maximum power dissipation
limit. Damage is prevented by clamping the noise filter voltage to less than
13-66 HP 70427A/HP 70428A User's Guide
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