HP 70427A User Manual page 466

Block Diagram
600 MHz Reference Loop (A7A2)
Digital Control
The digital interface with the rest of the module is through a serial three-line
data bus. The interface is implemented using a custom I/O interface chip.
The chip requires a bidirectional data line, a clock line and a chip
enable/interrupt line from the microprocessor. The I/O chip generates 22
parallel outputs and controls all the functions on the A2A7 board. The I/O
chip also latches and transfers the interrupt status of the out-of-lock detectors
to the microprocessor.
HP 70427A/HP 70428A User's Guide 13-31