HP 70427A User Manual page 445

Block Diagram
100 MHz Reference Loop (A7A1)
block is approximately 168 dB with a 3 V/rad phase detector sensitivity at
the amplifier output.
The phase detector amplifier output primarily feeds the 100 MHz loop
integrator. It is also connected to the module's diagnostic multiplexer system
and the 100 MHz PLL phase detector beatnote out-of-lock detector. The
beatnote detector is a window comparator. It monitors the phase detector
amplifier output voltage. An output voltage greater than +2.1 V or less than
–2.1 V indicates an out-of-lock condition which triggers the loop's integrator
acquisition circuit. The out-of-lock condition is also reported to the module's
microprocessor via a processor interrupt which activates an SRQ and ERR
status indicator on the front panel.
The diagnostic multiplexer system is a series of 8-input analog multiplexers
which allow the monitoring of key analog voltages and waveforms
throughout the module by the module's internal volt meter and external test
equipment connected to the MULTIPLEXER OUT on the module's rear
panel.
Loop Integrator/Search Acquisition
The loop integrator/search acquisition block controls the loop bandwidth,
monitors out-of-lock, causes the integrator to search and acquire lock, and
configures the VCXO between being phase-locked to the 10 MHz reference
and free running.
The 100 MHz reference clean-up loop is a second order PLL, with 8
selectable loop bandwidths. The multiple loop bandwidths are available to
optimize the noise performance trade-off between the multiplied 10 MHz
timebase noise and the 100 MHz VCXO.
Wider loop bandwidths track the multiplied 10 MHz signal more closely,
allowing for a faster tuning response to changes in the 10 MHz timebase.
This allows a phase noise measurement system to use a greater measurement
PLL bandwidth without producing excessive measurement loop peaking.
Excess measurement loop peaking is produced by the group delay caused by
insufficient tuneline bandwidth (tuning through a PLL with insufficient
bandwidth).
Narrower loop bandwidths take advantage of the 100 MHz VCXO noise
performance. The 100 MHz VCXO noise performance is better than the 10
MHz timebase multiplied to 100 MHz for offsets greater than approximately
120 Hz. Inside the PLL bandwidth, the loop tracks the noise of the
multiplied 10 MHz signal. Outside the PLL bandwidth, the noise
performance is that of the free running 100 MHz VCXO. The best
compromise from a noise standpoint is the default bandwidth of 126 Hz.
The noise at the edge of the loop bandwidth is actually the sum of the
reference noise and the VCXO noise, plus any loop peaking due to excess
phase shifts around the loop. The PLL bandwidth can be adjusted to
13-10 HP 70427A/HP 70428A User's Guide