HP 70427A User Manual page 462

L f ( )
where: V = noise voltage
rms
k = oscillator tuning sensitivity, and
v
F = carrier frequency offset.
m
The tuning port noise contribution is –167 dBc/Hz. The typical STWO
performance at 10 kHz offset is –163 dBc/Hz. The tuning port noise
degrades the performance to –161.5 dBc/Hz under closed loop conditions.
Four different integrator feedback networks produce the integrator
characteristics required for the four PLL bandwidths. All four feedback
networks are in parallel, and must be driven by the integrator op-amp's
output. An analog multiplexer selects which network is actually fed back to
the integrator op-amp. Stability in the integrator op-amp is maintained by
adding the 100 pF capacitor between the op-amp's negative input and output.
The 100 pF capacitor counter-acts the excess phase shift added by the analog
multiplexer.
The integrator's main output drives the four lead/lag networks required for
the four PLL bandwidths. The integrator output is also connected to the
diagnostic multiplexer system. A second analog multiplexer selects STWO
tuning port input. The multiplexer selects between the four lead/lag
networks, the CUST/INT tune line (20 ppm/V tuning sensitivity) and ground
(600 MHz NO TUNE).
The two analog multiplexers' control inputs are connected together so that
the first two bits of each multiplexer control the PLL bandwidths. The third
bit on the integrator multiplexer is grounded. This forces this multiplexer to
select only one of the four integrator feedback networks. The third bit of the
tuning port select multiplexer selects between the phase-locked modes and
the free running STWO modes.
The tuning port select analog multiplexer output is connected to four
locations. The main output is the 600 MHz STWO tune port. It is also
connected to the diagnostic multiplexer system, the integrator out-of-lock
detector, and the search/acquisition lead/lag network speed-up circuit.
The 4 kHz PLL bandwidth lead/lag network has a pole at 14.3 Hz which sets
the maximum rate at which the integrator may search to acquire phase-lock.
The speed-up circuit places a 511Ω resistor in parallel with the lead/lag
network's input resistor whenever the voltage difference across the network
exceeds ±0.4 V. This 511Ω resistor raises the pole frequency of the 4 kHz
lead/lag network to 64 Hz. This greatly increases the maximum rate at which
the integrator may search to acquire phase-lock.
600 MHz Reference Loop (A7A2)
V K
rms v
20 log
=
------------------- -
2F m
HP 70427A/HP 70428A User's Guide 13-27
Block Diagram