HP 70427A User Manual page 446

optimize the performance between 0.01 and 100 Hz by setting the bandwidth
to 300 Hz or greater. The noise performance greater than 100 Hz is
optimized by setting a narrow loop bandwidth (53 Hz or less) which still
retains the frequency stability and noise performance of the 10 MHz
timebase at very low carrier offsets. If noise performance less than 100 Hz is
not important, the best noise performance is achieved by tuning the 100
MHz VCXO directly (1 ppm/V tuning sensitivity).
The selectable PLL bandwidths range from 25 Hz to 10.4 kHz, with a
logarithmic distribution in an attempt to cover all required bandwidth
contingencies. The final bandwidths are 25 Hz, 53 Hz, 126 Hz, 300 Hz, 650
Hz, 1.53 kHz, 3.63 kHz and 10.4 kHz after adjusting for component
availability.
There are two primary assumptions that were made before the loop
integrator design could begin:
1. The phase detector gain is 3 V/rad. This is held constant by the
saturation output level of the phase detector mixer. Given that both
inputs to the phase detector (+7 dBm level) mixer is +5 to +10 dBm, the
saturated output is a 0.3 V/rad phase slope into a 50Ω termination. The
output is then amplified by 20 dB (10×) resulting in the 3 V/rad phase
detector gain. The 20 dB gain, low-noise amplifier is necessary to insure
that the signal levels out of the phase detector are large enough to
maintain an adequate signal-to-noise ratio, despite the added noise from
the integrator.
2. The VCXO tuning sensitivity is 155 Hz/V. This was determined
experimentally after there was a stable 100 MHz VCXO design with
adequate noise performance and tuning range. The original VCXO
design goal was a 100 Hz/V tuning sensitivity.
The first order, closed loop bandwidth, equals phase detector gain times
tuning sensitivity (3 V/rad * 15 Hz/V= 465 Hz).
The eight different PLL bandwidths are produced by switching between
eight different integrator networks. Each integrator network was designed as
follows:
a. Calculate the ratio between the first order closed loop bandwidth
and the desired bandwidth. This ratio is the amount of gain the
integrator must add to or subtract from the VCXO tuning sensitivity.
100 MHz Reference Loop (A7A1)
HP 70427A/HP 70428A User's Guide 13-11
Block Diagram