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frequency. The two responses will then cancel. What remains is the
integrator's response with the zero of the lead/lag network.
Each integrator-lead/lag network was designed as follows:
1. Calculate the ratio between the desired closed loop bandwidth and the
first order loop bandwidth. This ratio is the amount of gain the
integrator-lead/lag must add to or subtract from the STWO tuning
sensitivity. It is equal to:
(
BW desired
--------------------------------------------------- -
BW firs t order loop
(
2. Set the lead/lag zero at
peaking 2 dB or less due to the zero's phase shift.
BW desired
--------------------------------- -
3. Set the integrator's zero to the same frequency as the lead/lag's pole.
--------------------------------------- -
2πC 1 R 1
The 10 kHz bandwidth for the 600 MHz PLL was used as a design example.
The noise design goal for the 10 kHz phase noise is –160 dBc/Hz at 600
MHz. The oscillator tuning sensitivity is 10 kHz/V.
The tuning port noise contribution is to be 0.1 dB, so its noise must be
–180 dbc. Given that:
L
f ( )
and solving for V
, the noise on the tuning port must be 1.41 nV or less at
rms
10 kHz. This is the equivalent of a 123 Ω resistor at room temperature. This
is why R 4 is of this magnitude.
The oscillator's 10 kHz performance is excellent, and loop peaking would
not be tolerated, so the lead/lag zero was set at bandwidth ÷ 10. This
eliminates loop peaking, but does not yield enough loop gain at 1 kHz offset
to suppress the 1 kHz STWO noise to the multiplied 100 MHz reference
noise performance.
A 2 dB improvement in the 10 kHz noise performance is made at the
expense of a 2 dB degradation in the performance at 1 kHz.
600 MHz Reference Loop (A7A2)
)
=
Integrator gain
)
(
)
BW desired
or less to keep the loop
--------------------------------- -
4
(
)
1
=
-------------------------- -
(
4
2πR
C
4
1
1
=
--------------------------------------- -
(
)
(
+
R 2
2πC 2 R 3
20
log
V
K
rms
v
=
------------------------------------
2F
m
HP 70427A/HP 70428A User's Guide 13-23
Block Diagram
×
Lead\Lag Gain
)
2
)
+
R 4
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