HP 70427A User Manual page 449

Block Diagram
100 MHz Reference Loop (A7A1)
The integrator out-of-lock detector is a window comparator with its
threshold set at ±10 V. If the tune line voltage goes outside the ±10 V range,
an interrupt is generated in the microprocessor, and the search/acquisition
speed-up circuit is activated.
NOTE The 100 MHz PLL will remain phase-locked and on frequency with as much
as ±12.5 V on the tune line, but the noise and spur performance will be
greatly impaired. This circuitry is always active and can also act as an
over-voltage indicator for the 1 ppm/V tuning mode.
Search and acquisition is accomplished by ramping the integrator output
voltage to that voltage required by the VCXO to be at the same frequency as
the 100 MHz reference. The phase detector can then produce the phase-error
voltage necessary to produce and maintain phase-lock.
The search is produced by a small amount of positive feedback placed
around the loop's integrator. The positive feedback amplifier places an offset
voltage at the integrator input of + or – 0.15 volts. This offset voltage forces
the integrator's inverted output to ramp in voltage until it reaches a threshold
of – or + 12 V. When the threshold voltage is reached, the offset voltage is
reversed, forcing the integrator to ramp in voltage in the opposite direction.
The integrator output continues to search until either the tune line voltage
remains within the ±12 V window, as in 100 MHz NO TUNE and 1 ppm/V
modes, or there is enough negative feedback produced by the loop being
phase-locked to overcome the positive feedback. The amount of phase
detector offset required to overcome the positive feedback is 15 mV, about
.25 degrees of offset.
The search speed-up circuit increases the PLL bandwidth to at least 1200 Hz
when triggered by the out-of-lock detectors. This is done by placing a 10 kΩ
resistor in parallel with all the integrator input resistors. The sweep speed is
further increased by placing a 10 kΩ resistor in parallel with the positive
feedback offset resistor, raising the integrator offset to ±0.22 V.
The speed-up timer triggers for 100 ms, and is retriggered by the out-of-lock
detectors if lock is not acquired in that time period.
100 MHz Oscillator
The 100 MHz VCXO is a fifth overtone crystal oscillator designed for low
noise performance and wide tuning range. The tuning sensitivity is typically
155 Hz/V at 100 MHz or approximately 1 ppm/V. It is designed to oscillate
at 100 MHz, –1.125 kHz @ –10 V tune line voltage and +2.0 kHz @ + 10 V
tune line voltage. The exact frequency of oscillation is not important for
phase noise measurements, but the VCXO must be able to acquire and
maintain phase-lock under all environmental conditions with an external 10
MHz timebase, tunable over a ±1 ppm range, which is ±100 Hz at 100 MHz.
13-14 HP 70427A/HP 70428A User's Guide