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NOTE
Block Diagram
600 MHz Reference Loop (A7A2)
Using the 17 kHz bandwidth results in a 2 dB improvement in the 1 kHz
noise for a 3 dB degradation in the 10 kHz performance. An additional 3 dB
of improvement can be made to the 10 kHz noise performance using the 4
kHz bandwidth at the expense of 2 dB degradation to the 1 kHz noise.
Given the 10 kHz PLL bandwidth, and the lead/lag zero set to bandwidth ÷
10, the zero is 1 kHz. The lead/lag capacitor C
(
BW desired
--------------------------------- -
10
assuming R 4 is 125Ω, and solving for C
Adjusting for standard component values:
= 1 μF and
C
2
R
= 162Ω, with
4
F
= 982 Hz.
zero
The lead/lag pole is set at 1/10 the lead/lag zero frequency to provide 20 dB
of attenuation to the noise added by the integrator, approximately 100 Hz.
The lead/lag resistor R 3 can be calculated using:
(
BW desired
--------------------------------- -
100
assuming R
is 162Ω and C
4
Adjusting for standard component values:
R
= 1.47 kΩ,
3
= 1 μF and
C
2
R
= 162Ω, with
4
F
= 97.5 Hz
pole
and a gain of 0.0993 beyond F zero ,
where the lead/lag gain is:
Lead\Lag Gain
well beyond F
zero .
13-24 HP 70427A/HP 70428A User's Guide
can now be calculated using:
2
)
1
=
F
=
------------------------ -
(
zero
2πR
C
4
= 1.27 μF.
yields C
2
2
)
1
=
F
=
---------------------------------- -
(
zero
2πC R
is 1 μF, and solving for R
2
R
4
=
----------------------- -
(
)
+
R
R
3
4
)
2
)
+
R
3
4
yields R
= 1.43 kΩ.
3
3
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