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Block Diagram
100 MHz Reference Loop (A7A1)
current flow to change instantaneously, the inductor supplies the voltage
necessary to switch the diodes fast. The fast switching of the diodes
produces a square wave very rich in odd harmonics. The fifth harmonic
signal flows through the capacitor at the output of the impedance matching
network, through the bridge rectifier squaring circuit and out the series
resonant circuit at the multiplier output. The parallel resonant circuit to
ground is resonant at the fifth harmonic so it does not short the 100 MHz
signal to ground. The multiplier output level is about +3 dBm.
The 100 MHz signal is amplified by the 100 MHz multiplier output
amplifier. This 17 dB gain amplifier is designed to remain low noise when
driven into collector current cutoff. Its output level is about +11 to +15 dBm
into 50Ω. This 100 MHz signal is the phase detector reference for the 100
MHz reference clean-up loop.
Phase Detector/2.3 MHz LPF/20 dB Amp
The phase detector/amplifier block combines the 100 MHz reference output
with the output of the 100 MHz VCXO, through the 80 dB isolation
amplifier, to produce a phase error voltage. This phase error voltage will be
integrated, and then fed back to the VCXO to phase-lock the oscillator.
The phase detector is a doubly balanced mixer. One input is the 100 MHz
multiplier's output. The other input is a +5 to +7 dBm signal from the 80 dB
isolation amplifier. The two signals are multiplied together which produces a
sum and difference product. The 200 MHz sum product and the 100 MHz
feedthrough are terminated in 50Ω by the 2.3 MHz low pass filter's diplexed
input. The difference product is proportional to the phase error between the
two inputs, where a 90 degree phase difference between the two inputs will
produce 0 V output. The phase detector sensitivity is 0.3 V/rad.
The 2.3 MHz lowpass filter (LPF) performs two functions. First, it provides
the termination of undesired 100 and 200 MHz signals produced in the phase
detector. Second, it rejects the undesired harmonics of 10 MHz, produced in
the 10 to 100 MHz Multiplier, by 70 dB. These 10 MHz harmonics will
produce 10 MHz sidebands on the PLL output if allowed to reach the VCXO
tuning port.
The filter was designed in two sections. The input is a 3 pole, 0.1 dB ripple,
3 MHz Chebyshev LPF, with a 50Ω resistor in series with the input
capacitor. The 50Ω resistor terminates frequencies above the filter cutoff
frequency. The majority of the stop band performance is from the 5 pole, 2
zero, 3 MHz elliptic filter section. Phase delay in the LPF must be
minimized to prevent PLL peaking due to excess phase shift around the loop.
The output of the filter is terminated in 50Ω to provide proper filter
response.
The output of the LPF is amplified 20 dB by a low noise non- inverting
operational amplifier. The input noise of the op- amp is about 1.2 nV/Hz.
Given a 0.3 V/rad phase detector sensitivity, the signal-to-noise ratio of this
HP 70427A/HP 70428A User's Guide 13-9
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