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Overview
Looking at the Block
Diagram
Block Diagram
100 MHz Reference Loop (A7A1)
100 MHz Reference Loop (A7A1)
The 100 MHz Reference Loop multiplies the 10 MHz rear panel input to
100 MHz. This signal is the phase detector reference for the 100 MHz PLL.
The 100 MHz PLL filters out spurs from the 10× multiplier, and optimizes
the phase noise between the multiplied-up 10 MHz timebase and the loop's
100 MHz VCXO. The 100 MHz PLL's bandwidth is adjustable between
25 Hz and 10.4 kHz, in 8 steps. The default bandwidth is 126 Hz, which
produces the best noise compromise. Also, the front-panel voltage control
distribution switches for the 10, 100 and 600 MHz oscillators are also
implemented on the A7A1 PC board.
VCO Tuneline Control
The VCO tuneline control block provides the tuneline switching for the
module, and controls the Internal timebase A5Y1. There are two inputs to
this block. The primary input is the Voltage Control input from the front
panel of the module which allows the user or an HP 3048A Phase Noise
System to electronically tune the reference chain. The internal tuneline input
is not currently used. These two inputs are combined in an SPDT relay to
produce the CUST/INT TUNE which is selected by the 10, 100 and 600
MHz oscillators. The CUST/INT TUNE line also has a switchable, high
current, buffered output which is available from the rear panel. The output
impedance is 50Ω, with 100 mA current capability.
The input impedance is 100 kΩ on the front panel for the 1 ppm/V and 5
ppm/V tuning sensitivities. When the 0.05 ppm/V sensitivity is selected, the
10 MHz timebase's internal 38 kΩ tuneline resistor is placed in parallel with
the module's 100 kΩ input impedance, reducing the input impedance to 27.5
kΩ.
The voltage control input range is specified to be ±5 V, and usable to ±10 V.
The input is also clamped by diodes at ± 15 V to prevent damage to the solid
state switches by inputs exceeding the ±15 V supply voltage. The input
impedance for signals greater than ±15 V is 250Ω.
The VOLTAGE CONTROL MUST BE TERMINATED OR DRIVEN
WITH AN IMPEDANCE OF 50Ω OR LESS to prevent module noise
performance degradation due to excess resistor thermal noise voltage, in all
input tuning sensitivity modes except 0 ppm/V. The 50Ω termination also
greatly improves tuneline input offset voltage frequency error.
Both the timebase 10 MHz output, and EFC source are controlled by the
VCO tuneline control block. The 10 MHz output can be toggled on and off.
The timebase EFC is selectable between ground, for 0 ppm/V tuning
sensitivity, and the CUST/INT TUNE for 0.05 ppm/V tuning sensitivity.
13-6 HP 70427A/HP 70428A User's Guide
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