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Block Diagram
600 MHz Reference Loop (A7A2)
4 kHz BW
R
4.22 k
1
R
6.19 k
2
1 μF
C
1
R
2.15 k
3
R
82.5Ω
4
5 μF
C
2
Integrator
15.3 Hz
Zero
Lead/Lag
14.3 Hz
Pole
Lead/Lag
386 Hz
Pole
Solving for the integrator gain yields: Gain = 2.37. Assuming C
solving for R
and R
yields R
1
2
Adjusting for standard Component values:
C
= 1mF
1
Ω
R
= 619
1
Ω
R
= 909
2
Yields F
+ 104.2 Hz and a gain of 2.47 well beyond F
zero
bandwidth is 10.42 kHz.
Checking the tuning port noise performance, the input noise performance of
the phase detector amplifier op-amp is about 2 nV/Hz in its circuit
configuration. The maximum gain of the amplifier is 12.87, so the maximum
output noise is 25.5 nV/Hz. The integrator multiplies the phase detector
amplifier noise by 2.47, to produce 63 nV/Hz of noise at the integrator
output. The integrator op-amp input noise is 4 nV/Hz.
The integrator input noise is also multiplied by the integrator gain of 2.47, to
produce an output noise of 9.9 nV/Hz. The two noise mechanisms add as:
TotalNoise
The two mechanisms together produce 63.8 nV/Hz at the lead/lag network
input. The lead/lag network attenuates the noise to 6.33 nV/Hz by
multiplying the noise by its gain of 0.0993. The tuning port noise
contribution at 10 kHz carrier offset can be calculated by:
13-26 HP 70427A/HP 70428A User's Guide
Table 13-7
Gain Yields
10 kHz
17kHz BW
BW
619Ω
1.1 k
909Ω
4.64 k
1 μF
o.1 μF
1.47 k
2.61 k
162Ω
215Ω
1 μF
0.2 μF
104 Hz
277 Hz
97.5 Hz
282 Hz
982 Hz
3.70 Hz
Ω
= 689
and R2 + 944
1
2
(
)
(
=
+
noise1
noise2
30 kHz BW
562Ω
2.37 k
0.068 μF
1.47 k
215Ω
o.1 μF
798 Hz
944.5 Hz
7.40 Hz
μ
is 1
F, and
1
Ω
.
. The actual
zero
2
)
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