HP 70427A User Manual page 447

Block Diagram
100 MHz Reference Loop (A7A1)
It is equal to the ratio of the integrator output resistor divided by the
input resistor.
b. Set the integrator zero at BW(desired) / 4 to keep the loop peaking
less than 2 dB due to the zero's phase shift. . . . . . . . . . . . . . . . . . . .
Figure 13-2 100 MHz Phase Locked Loop Integrator
13-12 HP 70427A/HP 70428A User's Guide
( )
BW desired
---------------------------------------------------- =
( )
BW firs torderloop
( )
BW desired 1
--------------------------------- - = ------------------- -
4 2πR
(
R
2
---- -
R
1
C
)
2