HP 70427A User Manual page 452

Overview
Looking at the Block
Diagram
600 MHz Reference Loop (A7A2)
The 600 MHz reference Loop multiplies the 100 MHz reference loop's
output to 600 MHz. This signal is the phase detector reference for the
600 MHz clean-up PLL. The 600 MHz PLL filters out spurs from the 6×
multiplier, and optimizes the phase noise between the multiplied-up
100 MHz Reference loop, and the loop's 600 MHz
surface-transverse-wave-oscillator (STWO). The 600 MHz PLL's bandwidth
is adjustable between 4 kHz and 30 kHz, in 4 steps. The default bandwidth is
10 kHz, which produces the best noise compromise at a 1 kHz offset. The 10
kHz noise is improved by 3 dB using the 4 kHz PLL bandwidth. The 600
MHz PLL output is the reference for the microwave comb line generator.
The PLL also produces two auxiliary 600 MHz outputs available at the
module's rear panel.
100 MHz to 600 MHz Frequency Multiplier
The 100 to 600 MHz Multiplier Block multiplies the 100 MHz input from
the 100 MHz clean-up loop's main output by doubling the signal to
200 MHz, then multiplying by 3 to 600 MHz.
The signal from the 100 MHz PLL output drives the 2x doubler. The doubler
is implemented by splitting the 20 dBm, 100 MHz signal in a quadrature
hybrid. The two outputs are about +16 dBm, and 90 degrees out of phase.
The two signals are then mixed together in a double-balanced mixer. The
result is a small DC offset due to phase errors, and a signal at twice the input
frequency. The 200 MHz signal level is about +7 dBm. The 200 MHz
signal's 100 MHz feedthrough is about –30 dBc.
The 200 MHz signal is amplified by the 200 MHz interstage amplifier. This
amplifier has 16 dB gain with tuned output. Its output level is about +18
Ω.
dBm into 50 The amplifier must maintain good noise performance while
operating in gain compression.
600 MHz Reference Loop (A7A2)
HP 70427A/HP 70428A User's Guide 13-17
Block Diagram