Table of Contents
Advertisement
Block Diagram
600 MHz Reference Loop (A7A2)
The lead/lag speed-up circuit is engaged whenever the 600 MHz reference is
set for phase-locked operation.
The integrator out-of-lock detector is a window comparator with its
threshold set at ±10 V. If the tune line voltage goes outside the ±10 V range,
an interrupt is generated in the microprocessor, and the search/acquisition
circuit is activated.
CAUTION
The 600 MHz PLL will remain phase-locked and on frequency with as much
as ±12.5 V on the tune line, but the noise and spur performance will be
greatly impaired. This circuitry is always active and can also act as an
over-voltage indicator for the 20 ppm/V tuning mode.
Sweep-to-Lock
The sweep-to-lock circuit, when triggered by one of the out-of-lock
indicators, sweeps the loop integrator in an attempt to acquire phase lock.
The sweep in the voltage of the loop integrator sweeps the output frequency
of the loop, which is fed back through the phase detector. When the loop
output is at the same frequency as the 600 MHz reference, the phase detector
will produce the phase-error voltage necessary to acquire and maintain
phase-lock. When this occurs, the out-of-lock indicators will indicate a
locked condition.
The sweep-to-lock circuit is microprocessor controlled. It is normally active
whenever the 600 MHz reference is in a phase-locked mode. When active,
the sweep-to-lock circuit will accept a trigger signal from the integrator or
beat note out-of-lock indicators. The trigger signal from the out-of-lock
indicators is a level sensitive input, where a logical "0" is the out-of-lock
condition. The logical "0" trigger level activates a 9.4 kHz astable oscillator
which is necessary to activate the edge triggered sweep-to-lock circuit.
The sweep-to-lock circuit consists of a pair of one-shot monostable
multi-vibrator timers, each set for a 219 ms pulse. The first one-shot is
triggered by the 9.4 kHz oscillator. The one-shot's output is connected to an
analog switch which places an offset on the phase detector amplifier input,
which places a large offset on the integrator input, forcing the integrator to
ramp in voltage, in an attempt to acquire lock.
The end of the first time period triggers the second timer, which is also
connected to an analog switch. This switch produces a voltage offset in the
opposite direction forcing the integrator to ramp down in voltage, in a
second attempt to acquire phase lock. At the end of the second time period,
the out-of-lock indicator is checked for lock. If lock has not occurred, the
cycle repeats. Lock will normally occur in 500 ms.
The sweep-to-lock signals injected into the phase detector amplifier are
adjustable to two levels of integrator input offset. The normal level produces
±0.88 V of integrator input offset. It is used in the 10 kHz, 17 kHz and 30
13-28 HP 70427A/HP 70428A User's Guide
Advertisement
Table of Contents
