HP 70427A User Manual page 456

Block Diagram
600 MHz Reference Loop (A7A2)
acquisition circuit. The out-of-lock condition is also reported to the module's
microprocessor via a processor interrupt.
The diagnostic multiplexer system is a series of 8 input analog multiplexers
which allow the monitoring of key analog voltages and waveforms
throughout the module by the module's internal volt meter and external test
equipment connected to the MULTIPLEXER OUT connector on the
module's rear panel.
Loop Integrator
The loop integrator block controls the loop bandwidth, monitors out-of-lock,
and configures the STWO between being phase-locked to the 100 MHz
reference and free running.
The 600 MHz reference clean-up loop is a second order PLL, with 4
selectable loop bandwidths. The multiple loop bandwidths are available to
optimize the noise performance trade-off between the multiplied 100 MHz
reference noise and the 600 MHz STWO.
Wider loop bandwidths track the multiplied 100 MHz more closely, allowing
for a faster tuning response to changes in the 100 MHz reference. This
allows a phase noise measurement system to use a greater measurement PLL
bandwidth without producing excessive measurement loop peaking. Excess
measurement loop peaking is produced by the group delay caused by
insufficient tuneline bandwidth (tuning through a PLL with insufficient
bandwidth).
Narrower loop bandwidths take advantage of the 600 MHz STWO noise
performance. The 600 MHz STWO noise performance is better than the
100 MHz reference multiplied to 600 MHz for offsets greater than
approximately 10 kHz. Inside the PLL bandwidth, the loop tracks the noise
of the multiplied 100 MHz signal. Outside the PLL bandwidth, The noise
performance is that of the free running 600 MHz STWO. The best
compromise from a noise standpoint is the default bandwidth of 10 kHz.
The noise at the edge of the loop bandwidth is actually the sum of the
100 MHz reference noise multiplied to 600 MHz, the STWO noise and noise
added by the amplifiers and integrator in the 600 MHz PLL, plus any loop
peaking due to excess phase shifts around the loop. The PLL bandwidth can
be adjusted to optimize the performance between 0.01 and 10 kHz by setting
the bandwidth to 17 or 30 kHz. The noise performance greater than 10 kHz
is optimized by setting the loop bandwidth to 4 kHz, which still retains the
frequency stability and noise performance of the 100 MHz reference at low
carrier offsets below 4 kHz. If noise performance less than 10 kHz is not
important, the best noise performance is achieved by tuning the 600 MHz
STWO directly (5 ppm/V tuning sensitivity).
HP 70427A/HP 70428A User's Guide 13-21