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10 MHz to 100 MHz Frequency Multiplier
The 10 to 100 MHz multiplier block multiplies the 10 MHz input to
100 MHz by doubling the signal to 20 MHz, then multiplying by 5. It also
produces a switched, buffered 10 MHz rear-panel output.
The 10 MHz rear-panel signal is first amplified to about 18 dBm. This 10 dB
gain amplifier with tuned output is designed to be operated in compression
without adding significant noise to the 10 MHz input signal. The collector
supply is regulated with a capacitance multiplier to reduce power supply
noise that will be up-converted around the carrier. The RF amplifier is
designed to be limited by collector current cutoff, not V
The signal is then split.
The 10 MHz auxiliary output signal is picked off with a 511Ω resistor. The
signal is then amplified in a differential amplifier, followed by an emitter
follower, both for high isolation. The output is tuned to 10 MHz, via C42,
C43, and L12, to reduce harmonics. The output impedance is 50Ω with a
nominal power of +10 dBm.
The main signal from the input amplifier drives the 2x doubler. The doubler
is implemented by splitting the 18 dBm, 10 MHz signal in a quadrature
hybrid. The two outputs are about +14 dBm, and 90 degrees out of phase.
The two signals are then mixed together in a doubly balanced mixer. The
result is a small DC offset, due to phase errors, and a signal at twice the input
frequency. The 20 MHz signal level is about +5 dBm. The 20 MHz signal's
10 MHz feedthrough is about –30 dBc.
The 20 MHz signal is amplified by the 20 MHz interstage amplifier. This 17
dB gain amplifier has a tuned output to eliminate subharmonics and is very
similar to the 10 MHz input amplifier design, except for its gain and output
frequency. Its output level is about +18 dBm into 50
The 20 MHz interstage amplifier drives the 5× multiplier. The 5× multiplier
is based on the harmonic content of a square wave. Its theoretical efficiency
is as follows:
efficiency (dB) = 20 log (1/n)
where n = the desired harmonic
For example, If n=5, then efficiency= –14 dB.
The 5× multiplier works by first impedance transforming the 20 MHz input
signal to about 300Ω. This is done so that the input voltage is large enough to
switch the 20 V Schottky diodes. The impedance transformer output
capacitor is also a low impedance for the desired fifth harmonic. The diodes
are arranged as a full wave bridge rectifier, with an inductor across the "+
and – outputs". One of the "AC inputs" is connected to the input impedance
transformer output. The other "AC input" is connected to the parallel
resonator to ground and the series resonator output.
100 MHz Reference Loop (A7A1)
ce
Ω.
HP 70427A/HP 70428A User's Guide 13-7
Block Diagram
saturation voltage.
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