Renesas HD64F3039F Manuals

Manuals and User Guides for Renesas HD64F3039F. We have 1 Renesas HD64F3039F manual available for free PDF download: Hardware Manual

Renesas HD64F3039F Hardware Manual (708 pages)

16-Bit Single-Chip Microcomputer

Brand: Renesas | Category: Computer Hardware | Size: 3 MB

General Precautions in the Handling of MPU/MCU Products
3
Table of Contents
11
Section 1 Overview
23
Overview
23
Block Diagram
28
Pin Description
29
Pin Arrangement
29
Pin Functions
30
Pin Functions
34
Section 2 CPU
39
Overview
39
Features
39
Differences from H8/300 CPU
40
CPU Operating Modes
41
Address Space
42
Register Configuration
43
Overview
43
General Registers
44
Control Registers
45
Initial CPU Register Values
46
Data Formats
47
General Register Data Formats
47
Memory Data Formats
49
Instruction Set
50
Instruction Set Overview
50
Instructions and Addressing Modes
51
Tables of Instructions Classified by Function
53
Basic Instruction Formats
62
Notes on Use of Bit Manipulation Instructions
63
Addressing Modes and Effective Address Calculation
63
Addressing Modes
63
Effective Address Calculation
67
Processing States
71
Overview
71
Program Execution State
71
Exception-Handling State
72
Exception-Handling Sequences
73
Reset State
75
Power-Down State
75
Basic Operational Timing
76
Overview
76
On-Chip Memory Access Timing
76
On-Chip Supporting Module Access Timing
77
Access to External Address Space
78
Section 3 MCU Operating Modes
79
Overview
79
Operating Mode Selection
79
Register Configuration
80
Mode Control Register (MDCR)
81
System Control Register (SYSCR)
82
Operating Mode Descriptions
84
Mode 1
84
Mode 3
84
Mode 5
84
Mode 6
84
Mode 7
84
Pin Functions in each Operating Mode
85
Memory Map in each Operating Mode
85
Restrictions on Use of Mode 6
94
Section 4 Exception Handling
97
Overview
97
Exception Handling Types and Priority
97
Exception Handling Operation
97
Exception Vector Table
98
Reset
100
Overview
100
Reset Sequence
100
Interrupts after Reset
102
Interrupts
102
Trap Instruction
103
Stack Status after Exception Handling
103
Notes on Stack Usage
104
Section 5 Interrupt Controller
105
Overview
105
Features
105
Block Diagram
106
Pin Configuration
107
Register Configuration
107
Register Descriptions
108
System Control Register (SYSCR)
108
Interrupt Priority Registers a and B (IPRA, IPRB)
110
IRQ Status Register (ISR)
115
IRQ Enable Register (IER)
116
IRQ Sense Control Register (ISCR)
117
Interrupt Sources
118
External Interrupts
118
Internal Interrupts
119
Interrupt Vector Table
119
Interrupt Operation
122
Interrupt Handling Process
122
Interrupt Sequence
127
Interrupt Response Time
128
Usage Notes
129
Contention between Interrupt and Interrupt-Disabling Instruction
129
Instructions that Inhibit Interrupts
130
Interrupts During EEPMOV Instruction Execution
130
Usage Notes
130
Section 6 Bus Controller
133
Overview
133
Features
133
Block Diagram
134
Input/Output Pins
135
Register Configuration
135
Register Descriptions
136
Access State Control Register (ASTCR)
136
Wait Control Register (WCR)
137
Wait State Controller Enable Register (WCER)
138
Address Control Register (ADRCR)
139
Operation
141
Area Division
141
Bus Control Signal Timing
143
Wait Modes
145
Interconnections with Memory (Example)
151
Usage Notes
153
Register Write Timing
153
Precautions on Setting ASTCR and ABWCR
153
Section 7 I/O Ports
155
Overview
155
Port 1
159
Overview
159
Register Descriptions
160
Pin Functions in each Mode
162
Port 2
164
Overview
164
Register Descriptions
165
Pin Functions in each Mode
167
Input Pull-Up Transistors
169
Port 3
170
Overview
170
Register Descriptions
170
Pin Functions in each Mode
172
Port 5
174
Overview
174
Register Descriptions
175
Pin Functions in each Mode
177
Input Pull-Up Transistors
178
Port 6
179
Overview
179
Register Descriptions
180
Pin Functions in each Mode
182
Port 7
185
Overview
185
Register Description
185
Port 8
186
Overview
186
Register Descriptions
187
Pin Functions
189
Port 9
190
Overview
190
Register Descriptions
190
Pin Functions
192
Port a
194
Overview
194
Register Descriptions
195
Pin Functions
197
Port B
204
Overview
204
Pin Functions
206
Section 8 16-Bit Integrated Timer Unit (ITU)
213
Overview
213
Features
213
Block Diagrams
216
Input/Output Pins
221
Register Configuration
223
Register Descriptions
226
Timer Start Register (TSTR)
226
Timer Synchro Register (TSNC)
228
Timer Mode Register (TMDR)
230
Timer Function Control Register (TFCR)
233
Timer Output Master Enable Register (TOER)
236
Timer Output Control Register (TOCR)
238
Timer Counters (TCNT)
240
General Registers (GRA, GRB)
241
Buffer Registers (BRA, BRB)
242
Timer Control Registers (TCR)
243
Timer I/O Control Register (TIOR)
245
Timer Status Register (TSR)
247
Timer Interrupt Enable Register (TIER)
249
CPU Interface
250
16-Bit Accessible Registers
250
8-Bit Accessible Registers
253
Operation
254
Overview
254
Basic Functions
256
Synchronization
265
PWM Mode
267
Reset-Synchronized PWM Mode
271
Complementary PWM Mode
274
Phase Counting Mode
283
Buffering
285
ITU Output Timing
291
Interrupts
294
Setting of Status Flags
294
Clearing of Status Flags
296
Interrupt Sources
297
Usage Notes
298
Section 9 Programmable Timing Pattern Controller
313
Overview
313
Features
313
Block Diagram
314
TPC Pins
315
Registers
316
Register Descriptions
317
Port a Data Direction Register (PADDR)
317
Port a Data Register (PADR)
317
Port B Data Direction Register (PBDDR)
318
Port B Data Register (PBDR)
318
Next Data Register a (NDRA)
319
Next Data Register B (NDRB)
321
Next Data Enable Register a (NDERA)
323
Next Data Enable Register B (NDERB)
324
TPC Output Control Register (TPCR)
325
TPC Output Mode Register (TPMR)
328
Operation
330
Overview
330
Output Timing
331
Normal TPC Output
332
Non-Overlapping TPC Output
334
TPC Output Triggering by Input Capture
336
Usage Notes
337
Operation of TPC Output Pins
337
Note on Non-Overlapping Output
337
Section 10 Watchdog Timer
339
Overview
339
Features
339
Block Diagram
340
Pin Configuration
340
Register Configuration
341
Register Descriptions
341
Timer Counter (TCNT)
341
Timer Control/Status Register (TCSR)
342
Reset Control/Status Register (RSTCSR)
344
Notes on Register Access
346
Operation
348
Watchdog Timer Operation
348
Interval Timer Operation
349
Timing of Setting of Overflow Flag (OVF)
350
Timing of Setting of Watchdog Timer Reset Bit (WRST)
351
Interrupts
351
Usage Notes
352
Section 11 Serial Communication Interface
353
Overview
353
Features
353
Block Diagram
355
Input/Output Pins
356
Register Configuration
357
Register Descriptions
358
Receive Shift Register (RSR)
358
Receive Data Register (RDR)
358
Transmit Shift Register (TSR)
359
Transmit Data Register (TDR)
359
Serial Mode Register (SMR)
360
Serial Control Register (SCR)
363
Serial Status Register (SSR)
367
Bit Rate Register (BRR)
371
Operation
380
Overview
380
Operation in Asynchronous Mode
382
Multiprocessor Communication
391
Synchronous Operation
398
SCI Interrupts
406
Usage Notes
407
Section 12 Smart Card Interface
413
Overview
413
Features
413
Block Diagram
414
Pin Configuration
415
Register Configuration
415
Register Descriptions
416
Smart Card Mode Register (SCMR)
416
Serial Status Register (SSR)
418
Operation
419
Overview
419
Pin Connections
420
Data Format
421
Register Settings
423
Clock
425
Data Transfer Operations
427
Usage Note
433
Section 13 A/D Converter
437
Overview
437
Features
437
Block Diagram
438
Input Pins
439
Register Configuration
440
Register Descriptions
441
A/D Data Registers a to D (ADDRA to ADDRD)
441
A/D Control/Status Register (ADCSR)
442
A/D Control Register (ADCR)
444
CPU Interface
445
Operation
446
Single Mode (SCAN = 0)
446
Scan Mode (SCAN = 1)
448
Input Sampling and A/D Conversion Time
450
External Trigger Input Timing
451
Interrupts
452
Usage Notes
452
Section 14 RAM
457
Overview
457
Block Diagram
458
Register Configuration
458
System Control Register (SYSCR)
459
Operation
460
Section 15 ROM
461
Overview
461
Overview of Flash Memory
462
Features
462
Block Diagram
463
Pin Configuration
464
Register Configuration
464
Register Descriptions
465
Flash Memory Control Register (FLMCR)
465
Erase Block Register (EBR)
469
RAM Control Register (RAMCR)
471
Flash Memory Status Register (FLMSR)
473
On-Board Programming Modes
474
Boot Mode
477
User Program Mode
482
Programming/Erasing Flash Memory
484
Program Mode
485
Program-Verify Mode
486
Erase Mode
488
Erase-Verify Mode
488
Flash Memory Protection
490
Hardware Protection
490
Software Protection
492
Error Protection
493
NMI Input Disable Conditions
495
Flash Memory Emulation by RAM
496
Flash Memory PROM Mode
497
PROM Mode Setting
497
Memory Map
498
PROM Mode Operation
498
Memory Read Mode
501
Auto-Program Mode
504
Auto-Erase Mode
506
Status Read Mode
507
PROM Mode Transition Time
509
Notes on Memory Programming
510
Notes on Flash Memory Programming/Erasing
510
Mask ROM Overview
516
15.10.1 Block Diagram
516
Notes on Ordering Mask ROM Version Chip
517
Section 16 Clock Pulse Generator
519
Overview
519
Block Diagram
520
Oscillator Circuit
520
Connecting a Crystal Resonator
521
External Clock Input
523
Duty Adjustment Circuit
526
Prescalers
526
Frequency Divider
526
Register Configuration
526
Division Control Register (DIVCR)
527
Usage Notes
528
Section 17 Power-Down State
529
Overview
529
Register Configuration
531
System Control Register SYSCR
531
Module Standby Control Register (MSTCR)
533
Sleep Mode
535
Transition to Sleep Mode
535
Exit from Sleep Mode
535
Software Standby Mode
536
Transition to Software Standby Mode
536
Exit from Software Standby Mode
536
Selection of Oscillator Waiting Time after Exit from Software Standby Mode
537
Crystal Resonator
537
External Clock
537
Sample Application of Software Standby Mode
538
Usage Note
538
Hardware Standby Mode
539
Transition to Hardware Standby Mode
539
Exit from Hardware Standby Mode
539
Timing for Hardware Standby Mode
540
Module Standby Function
541
Module Standby Timing
541
Read/Write in Module Standby
541
Usage Notes
541
System Clock Output Disabling Function
542
Section 18 Electrical Characteristics
543
Electrical Characteristics of Mask ROM Version
543
Absolute Maximum Ratings
543
DC Characteristics
544
AC Characteristics
552
A/D Conversion Characteristics
557
Electrical Characteristics of Flash Memory Version
558
Absolute Maximum Ratings
558
DC Characteristics
559
AC Characteristics
565
A/D Conversion Characteristics
570
Flash Memory Characteristics
571
Operational Timing
574
Bus Timing
574
Control Signal Timing
578
Clock Timing
580
Oscillator Settling Timing
580
TPC and I/O Port Timing
580
ITU Timing
581
SCI Input/Output Timing
582
Appendix A Instruction Set
583
Instruction List
583
Data Transfer Instructions
585
Logic Instructions
591
Shift Instructions
592
Bit Manipulation Instructions
593
Branching Instructions
595
System Control Instructions
597
Operation Code Maps
599
Number of States Required for Execution
602
Appendix B Internal I/O Register Field
612
Addresses
612
Function
619
Appendix C I/O Block Diagrams
677
Port 1 Block Diagram
677
Port 2 Block Diagram
678
Port 3 Block Diagram
679
Port 5 Block Diagram
680
Port 6 Block Diagram
681
Port 7 Block Diagram
683
Port 8 Block Diagram
684
Port 9 Block Diagram
686
Port a Block Diagram
690
Port B Block Diagram
693
Appendix D Pin States
696
Port States in each Mode
696
Pin States at Reset
698
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode
701
Appendix F Product Lineup
702
Appendix G Package Dimensions
703

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