Honeywell Series A User Manual page 354

8. Maintenance, Checkout, and Calibration
8.10. FIM Self-Test Diagnostic Codes
Test Code Target Device(s)
Interrupt Test
ICP ASIC and Shared RAM Diagnostics
T100 ICP ASIC
Initialization Test
T101 ICP RAM Byte
Access Test
T102 ICP RAM Parity
Interrupt Test
T103
ICP RAM Word
Read Test
T104
ICP RAM Byte
Read Test
T105
ICP RAM Byte
Read Test
T106
ICP RAM Half Write
Test
T107 ICP RAM Half Align
Test
T108
ICP RAM Word
Align Test
T109
ICP RAM Unique
Address Test
354 Experion PKS Series A Fieldbus Interface Module User's Guide
Failure Modes
daughterboard is not asserted.
ICP ASIC, ICP, Insures that ICP_Fault signal is
Oscillator, PLD, asserted as IRQ1, releases ICP
CPU ASIC from RESET, insures that
ICP_FAULT clears within a
appropriate amount of time, writes
hardware initialization parameters
to ASIC, insures that ICP_FAULT
is not asserted.
RAM, PLD, CPU, Verifies that writing a string of 8
buffers bytes can be read back bytes and
as 2 correct words.
RAM, PLD, CPU, Prove that a shared RAM parity
buffers error can be genereated and
recognized by the CPU for
odd/even parity bit on each byte
lane. Shared RAM parity is
enabled from this test on.
RAM, PLD, CPU, Verifies that word patterns can be
buffers written and read back as words.
RAM, PLD, CPU, Verifies that word patterns can be
buffers written and read backs a bytes.
RAM, PLD, CPU, Verifies that word patterns can be
buffers written and read back as
halfwords.
RAM, PLD, CPU, Verifies that halfwords can be
buffers written.
RAM, PLD, CPU, Verifies that halfwords can be
buffers written, misaligned, and read back
as halfwords and words.
RAM, PLD, CPU, Verifies that words can be written
buffers and read when misaligned.
RAM, PLD, CPU, Verifies that each address can be
buffers accessed uniquely. Runs with data
parity enabled and fatal.
Honeywell
Function
R400
July 2010