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TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
4.17 External Clock Input From Oscillator or CLKIN Pin
The C672x device includes two choices to provide an external clock input, which is fed to the on-chip PLL
to generate high-frequency system clocks. These options are illustrated in
Figure 4-42
(a) illustrates the option that uses an on-chip 1.2-V oscillator with external crystal circuit.
Figure 4-42
(b) illustrates the option that uses an external 3.3-V LVCMOS-compatible clock input with
the CLKIN pin.
Note that the two clock inputs are logically combined internally before the PLL so the clock input that is not
used must be tied to ground.
C
5
C
7
X
1
R
C
8
R
S
C
6
If the on-chip oscillator is chosen, then the recommended component values for
in
Table
4-38.
FREQUENCY
XTAL TYPE
22.579
AT-49
22.579
SMD-49
24.576
AT-49
24.576
SMD-49
(1) Capacitors C
and C
are used to reduce oscillator jitter, but are optional. If C
5
6
capacitors C
and C
should be tied to OSCV
7
8
100
Peripheral and Electrical Specifications
OSCV
DD
OSCIN
B
OSCOUT
OSCV
SS
CLKIN
On-Chip 1.2-V Oscillator
(a)
Figure 4-42. C672x Clock Input Options
Table 4-38. Recommended On-Chip Oscillator Components
X
1
KDS 1AF225796A
KDS 1AS225796AG
KDS 1AF245766AAA
KDS 1AS245766AHA
and OSCV
SS
CV
(1.2 V)
DD
Clock
Input
NC
From
OSCIN
to
PLL
External 3.3-V LVCMOS-Compatible Clock Source
(1)
(1)
C
C
5
6
470 pF
470 pF
470 pF
470 pF
470 pF
470 pF
470 pF
470 pF
and C
are not used, then the node connecting
5
6
should be tied to CV
.
DD
DD
Figure
4-42.
OSCV
DD
OSCIN
OSCOUT
OSCV
SS
CLKIN
(b)
Figure 4-42
C
C
R
7
8
B
8 pF
8 pF
1 M
8 pF
8 pF
1 M
8 pF
8 pF
1 M
8 pF
8 pF
1 M
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Clock
Input
From
CLKIN
to
PLL
(a) are listed
R
S
0
0
0
0
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