Texas Instruments TMS320C6722 User Manual page 60

TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
The UHPI has several device-level configuration registers which affect its behavior.
Figure 4-19, and
Table 4-14 contain a description of the bits in these registers.
31
7
Reserved
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-12. CFGHPI Register Bit Field Description (0x4000 0008)
BIT NO. NAME
31:5 Reserved
4 BYTEAD
3 FULL
2 NMUX
1 PAGEM
0 ENA
60 Peripheral and Electrical Specifications
Figure 4-20 show the bit layout of these registers.
5 4
BYTEAD
R/W, 0
Figure 4-18. CFGHPI Register Bit Layout (0x4000 0008)
RESET READ
VALUE WRITE
N/A N/A Reads are indeterminate. Only 0s should be written to these bits.
0 R/W UHPI Host Address Type
0 = Host Address is a word address
1 = Host Address is a byte address
0 R/W UHPI Multiplexing Mode (when NMUX = 0)
0 = Half-Word (16-bit data) Multiplexed Address and Data Mode
1 = Fullword (32-bit data) Multiplexed Address and Data Mode
0 R/W UHPI Non-Multiplexed Mode Enable
0 = Multiplexed Address and Data Mode
1 = Non-Multiplexed Address and Data Mode (utilizes optional UHPI_HA[15:0] pins).
Host data bus is 32 bits in Non-Multiplexed mode. Setting this bit prevents the EMIF
from driving data out or 'parking' the shared EM_D[31:16]/UHPI_HA[15:0] pins.
0 R/W UHPI Page Mode Enable (Only for Multiplexed Address and Data Mode).
0 = Full 32-bit DSP address specified through host port.
1 = Only lower 16 bits of DSP address are specified through host port. Upper 16 bits
are restricted to the page selected by CFGHPIAMSB and CFGHPIAUMB registers.
0 R/W UHPI Enable
0 = UHPI is disabled
1 = UHPI is enabled. Set this bit to '1' only after configuring the other bits in this
register.
Reserved
3
FULL NMUX
R/W, 0 R/W, 0
DESCRIPTION
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Figure
Table 4-12, Table
2 1
PAGEM
R/W, 0
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4-18,
4-13, and
8
0
ENA
R/W, 0