Texas Instruments TMS320C6722 User Manual page 63

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Table 4-16. UHPI Read and Write Switching Characteristics
NO.
1 t Delay time, DS low to HD valid
d(DSL-HDV)
2 t Disable time, HD high-impedance from DS high
dis(DSH-HDV)
3 t Enable time, HD driven from DS low
en(DSL-HDD)
4 t Delay time, DS low to UHPI_HRDY high
d(DSL-HRDYH)
5 t Delay time, DS high to UHPI_HRDY high
d(DSH-HRDYH)
Delay time, DS low to UHPI_HRDY
6 t
d(DSL-HRDYL)
low
7 t Delay time, HD valid to UHPI_HRDY low
d(HDV-HRDYL)
Delay time, DS high to
34 t
d(DSH-HRDYL)
UHPI_HRDY low
Delay time, DS low to UHPI_HRDY low for HPIA write and FIFO not
35 t
d(DSL-HRDYL)
empty
36 t Delay time, UHPI_HAS low to UHPI_HRDY high
d(HASL-HRDYH)
(1) H = 0.5 * SYSCLK2 period
(2) DS refers to HSTROBE. HAD refers to UHPI_HCNTL[0], UHPI_HCNTL[1], UHPI_HHWIL, and UHPI_HRW.
(3) Max delay is a best case, assuming no delays due to resource conflicts between UHPI and dMAX or CPU. UHPI_HRDY should always
be used to indicate when an access is complete instead of relying on these parameters.
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PARAMETER
Case 1. HPIC or HPIA read
Case 2. HPID read with no
auto-increment
Case 3. HPID read with
auto-increment and read FIFO
initially empty
Case 4. HPID read with
auto-increment and data previously
prefetched into the read FIFO
Case 1. HPID read with no
auto-increment
Case 2. HPID read with
auto-increment and read FIFO
initialy empty
Case 1. HPIA write
Case 2. HPID read with
auto-increment and read FIFO
initially empty
TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
(1) (2)
MIN
1
1
1
3
0
Peripheral and Electrical Specifications
MAX UNIT
15
(3)
9 * 2H + 20
ns
(3)
9 * 2H + 20
15
4 ns
15 ns
12 ns
12 ns
(3)
10 * 2H + 20
ns
(3)
10 * 2H + 20
ns
(3)
5 * 2H + 20
ns
(3)
5 * 2H + 20
(3)
40 * 2H + 20 ns
12 ns
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