Texas Instruments TMS320C6722 User Manual page 87

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Table 4-30. Additional
NO.
Delay from final
24 t SPIx_CLK edge to slave
d(SPC_ENAH)S
deasserting SPIx_ENA.
(1) These parameters are in addition to the general timings for SPI slave modes
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
Table 4-31. Additional
NO.
Required delay from SPIx_SCS asserted at slave to first
25 t
d(SCSL_SPC)S
SPIx_CLK edge at slave.
Required delay from final
26 t SPIx_CLK edge before
d(SPC_SCSH)S
SPIx_SCS is deasserted.
Delay from master asserting SPIx_SCS to slave driving
27 t
ena(SCSL_SOMI)S
SPIx_SOMI valid
Delay from master deasserting SPIx_SCS to slave 3-stating
28 t
dis(SCSH_SOMI)S
SPIx_SOMI
(1) These parameters are in addition to the general timings for SPI slave modes
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
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TMS320C6727, TMS320C6726, TMS320C6722
(1)
SPI Slave Timings, 4-Pin Enable Option
Polarity = 0, Phase = 0,
from SPIx_CLK falling
Polarity = 0, Phase = 1,
from SPIx_CLK falling
Polarity = 1, Phase = 0,
from SPIx_CLK rising
Polarity = 1, Phase = 1,
from SPIx_CLK rising
(1)
SPI Slave Timings, 4-Pin Chip Select Option
Polarity = 0, Phase = 0,
from SPIx_CLK falling
Polarity = 0, Phase = 1,
from SPIx_CLK falling
Polarity = 1, Phase = 0,
from SPIx_CLK rising
Polarity = 1, Phase = 1,
from SPIx_CLK rising
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
(2) (3)
MIN
P – 10
0.5t + P – 10
c(SPC)M
P – 10
0.5t + P – 10
c(SPC)M
(Table 4-26).
0.5t + P + 10
c(SPC)M
P + 10
0.5t + P + 10
c(SPC)M
P + 10
(Table 4-26).
Peripheral and Electrical Specifications
MAX UNIT
3P + 15
0.5t + 3P + 15
c(SPC)M
ns
3P + 15
0.5t + 3P + 15
c(SPC)M
(2) (3)
MIN MAX UNIT
P ns
ns
P + 15 ns
P + 15 ns
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