Texas Instruments TMS320C6722 User Manual page 79

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AHCLKR/X (Falling Edge Polarity)
AHCLKR/X (Rising Edge Polarity)
ACLKR/X (CLKRP = CLKXP = 1)
ACLKR/X (CLKRP = CLKXP = 0)
AFSR/X (Bit Width, 0 Bit Delay)
AFSR/X (Bit Width, 1 Bit Delay)
AFSR/X (Bit Width, 2 Bit Delay)
AFSR/X (Slot Width, 0 Bit Delay)
AFSR/X (Slot Width, 1 Bit Delay)
AFSR/X (Slot Width, 2 Bit Delay)
AXR[n] (Data Out/Transmit)
A. For CLKRP = CLKXP = 1, the McASP transmitter is configured for falling edge (to shift data out) and the McASP
receiver is configured for rising edge (to shift data in).
B. For CLKRP = CLKXP = 0, the McASP transmitter is configured for rising edge (to shift data out) and the McASP
receiver is configured for falling edge (to shift data in).
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10
9
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(A)
(B)
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A0 A1
Figure 4-30. McASP Output Timings
TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
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13
A30 A31 B0 B1 B30 B31 C0
Peripheral and Electrical Specifications
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C1 C2 C3 C31
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