Device Configurations; Device Configuration Registers; Peripheral Pin Multiplexing Options - Texas Instruments TMS320C6722 User Manual

TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007

3 Device Configurations

3.1 Device Configuration Registers

The C672x DSP includes several device-level configuration registers, which are listed in
registers need to be programmed as part of the device initialization procedure. See
REGISTER NAME BYTE ADDRESS
CFGPIN0 0x4000 0000
CFGPIN1 0x4000 0004
CFGHPI 0x4000 0008
CFGHPIAMSB 0x4000 000C
CFGHPIAUMB 0x4000 0010
CFGRTI 0x4000 0014
CFGMCASP0 0x4000 0018
CFGMCASP1 0x4000 001C
(1)
CFGMCASP2 0x4000 0020
CFGBRIDGE 0x4000 0024
(1) CFGMCASP2 is reserved on the C6722.

3.2 Peripheral Pin Multiplexing Options

This section describes the options for configuring peripherals which share pins on the C672x DSP.
Table 3-2 lists the options for configuring the SPI0, I2C0, and I2C1 peripheral pins.
PERIPHERAL SPI0
I2C0
I2C1
PINS SPI0_SOMI/I2C0_SDA
SPI0_SIMO
SPI0_CLK/I2C0_SCL
SPI0_SCS/I2C1_SCL
SPI0_ENA/I2C1_SDA
30 Device Configurations
Table 3-1. Device-Level Configuration Registers
Captures values of eight pins on rising edge of RESET pin.
Captures values of eight pins on rising edge of RESET pin.
Controls enable of UHPI and selection of its operating mode.
Controls upper byte of UHPI address into C672x address space in
Non-Multiplexed Mode or if explicitly enabled for security purposes.
Controls upper middle byte of UHPI address into C672x address space
in Non-Multiplexed Mode or if explicitly enabled for security purposes.
Selects the sources for the RTI Input Captures from among the six
McASP DMA events.
Selects the peripheral pin to be used as AMUTEIN0.
Selects the peripheral pin to be used as AMUTEIN1.
Selects the peripheral pin to be used as AMUTEIN2.
Controls reset of the bridge BR2 in
explicitly after any change to the PLL controller affecting SYSCLK1 and
SYSCLK2 and before the dMAX or UHPI accesses the CPU Slave Port
(CSP).
Table 3-2. Options for Configuring SPI0, I2C0, and I2C1
OPTION 1
3-, 4,- or 5-pin mode 3-pin mode
disabled
disabled
SPI0_SOMI
SPI0_SIMO
SPI0_CLK
SPI0_SCS
SPI0_ENA
DESCRIPTION
Figure 2-4. This bridge must be reset
CONFIGURATION
OPTION 2
disabled
disabled enabled
enabled enabled
SPI0_SOMI I2C0_SDA
SPI0_SIMO GPIO through SPI0_SIMO pin control
SPI0_CLK I2C0_SCL
I2C1_SCL I2C1_SCL
I2C1_SDA I2C1_SDA
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Table 3-1. These
Section 3.2.
DEFINED
Table 2-10
Table 2-11
Table 4-12
Table 4-13
Table 4-14
Table 4-37
Table 4-19
Table 4-20
Table 4-21
Table 2-7
OPTION 3
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