Texas Instruments TMS320C6722 User Manual page 98

TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
The digital watchdog is disabled by default. Once enabled, a sequence of two 16-bit key values (0xE51A
followed by 0xA35C in two separate writes) must be continually written to the key register before the
watchdog counter counts down to zero; otherwise, the DSP will be reset. This feature can be used to
provide an added measure of robustness against a software failure. If the application fails and ceases to
write to the watchdog key; the watchdog will respond by resetting the DSP and thereby restarting the
application.
Note that Counter 0 and Compare 0 are used by DSP BIOS to generate the tick counter it requires;
however, Capture 0 is still available for use by the application as well as the remaining RTI resources.
4.16.2 RTI/Digital Watchdog Registers Description(s)
Table 4-36 is a list of the RTI registers.
BYTE ADDRESS
0x4000 0014 CFGRTI
0x4200 0000 RTIGCTRL
0x4200 0004 Reserved
0x4200 0008 RTICAPCTRL
0x4200 000C RTICOMPCTRL
0x4200 0010 RTIFRC0
0x4200 0014 RTIUC0
0x4200 0018 RTICPUC0
0x4200 0020 RTICAFRC0
0x4200 0024 RTICAUC0
0x4200 0030 RTIFRC1
0x4200 0034 RTIUC1
0x4200 0038 RTICPUC1
0x4200 0040 RTICAFRC1
0x4200 0044 RTICAUC1
0x4200 0050 RTICOMP0
0x4200 0054 RTIUDCP0
0x4200 0058 RTICOMP1
0x4200 005C RTIUDCP1
0x4200 0060 RTICOMP2
0x4200 0064 RTIUDCP2
0x4200 0068 RTICOMP3
0x4200 006C RTIUDCP3
0x4200 0070 Reserved
0x4200 0074 Reserved
0x4200 0080 RTISETINT
0x4200 0084 RTICLEARINT
98 Peripheral and Electrical Specifications
Table 4-36. RTI Registers
REGISTER NAME
Device-Level Configuration Registers Controlling RTI
Selects the sources for the RTI input captures from among the six McASP DMA event.
RTI Internal Registers
Global Control Register. Starts / stops the counters.
Reserved bit.
Capture Control. Controls the capture source for the counters.
Compare Control. Controls the source for the compare registers.
Free-Running Counter 0. Current value of free-running counter 0.
Up-Counter 0. Current value of prescale counter 0.
Compare Up-Counter 0. Compare value compared with prescale counter 0.
Capture Free-Running Counter 0. Current value of free-running counter 0 on external
event.
Capture Up-Counter 0. Current value of prescale counter 0 on external event.
Free-Running Counter 1. Current value of free-running counter 1.
Up-Counter 1. Current value of prescale counter 1.
Compare Up-Counter 1. Compare value compared with prescale counter 1.
Capture Free-Running Counter 1. Current value of free-running counter 1 on external
event.
Capture Up-Counter 1. Current value of prescale counter 1 on external event.
Compare 0. Compare value to be compared with the counters.
Update Compare 0. Value to be added to the compare register 0 value on compare
match.
Compare 1. Compare value to be compared with the counters.
Update Compare 1. Value to be added to the compare register 1 value on compare
match.
Compare 2. Compare value to be compared with the counters.
Update Compare 2. Value to be added to the compare register 2 value on compare
match.
Compare 3. Compare value to be compared with the counters.
Update Compare 3. Value to be added to the compare register 3 value on compare
match.
Reserved bit.
Reserved bit.
Set Interrupt Enable. Sets interrupt enable bits int RTIINTCTRL without having to do a
read-modify-write operation.
Clear Interrupt Enable. Clears interrupt enable bits int RTIINTCTRL without having to
do a read-modify-write operation.
DESCRIPTION
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