Texas Instruments TMS320F2809 Data Manual
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Texas Instruments TMS320F2809 Data Manual

Digital signal processors
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TMS320F2809, TMS320F2808, TMS320F2806
TMS320F2802, TMS320F2801, TMS320C2802
TMS320C2801, TMS320F28016, TMS320F28015
Digital Signal Processors
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SPRS230N
October 2003 – Revised May 2012

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  • Page 1 TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802 TMS320C2801, TMS320F28016, TMS320F28015 Digital Signal Processors Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

  • Page 2: Table Of Contents

    Enhanced QEP Modules (eQEP1/2) ............... Enhanced Analog-to-Digital Converter (ADC) Module ..............4.6.1 ADC Connections if the ADC Is Not Used ....................4.6.2 ADC Registers ........Enhanced Controller Area Network (eCAN) Modules (eCAN-A and eCAN-B) Contents Copyright © 2003–2012, Texas Instruments Incorporated...
  • Page 3 6.10.7.4 Simultaneous Sampling Mode (Dual-Channel) (SMODE = 1) ....................6.11 Detailed Descriptions ......................6.12 Flash Timing ....................6.13 ROM Timing (C280x only) ..............Migrating From F280x Devices to C280x Devices ......................Migration Issues ......................Revision History ......................Mechanical Data Contents Copyright © 2003–2012, Texas Instruments Incorporated...
  • Page 4 Typical Operational Current Versus Frequency (C280x) ..............Typical Operational Power Versus Frequency (C280x) .............. Emulator Connection Without Signal Buffering for the DSP ......................3.3-V Test Load Circuit ........................Clock Timing ......................... Power-on Reset List of Figures Copyright © 2003–2012, Texas Instruments Incorporated...
  • Page 5 SPI Slave Mode External Timing (Clock Phase = 1) ................... 6-24 ADC Power-Up Control Bit Timing ..................6-25 ADC Analog Input Impedance Model ..............6-26 Sequential Sampling Mode (Single-Channel) Timing ..................6-27 Simultaneous Sampling Mode Timing List of Figures Copyright © 2003–2012, Texas Instruments Incorporated...
  • Page 6 Typical Current Consumption by Various Peripherals (at 100 MHz) ............. TMS320x280x Clock Table and Nomenclature (100-MHz Devices) ..........TMS320x280x/2801x Clock Table and Nomenclature (60-MHz Devices) ......................Input Clock Frequency ................XCLKIN Timing Requirements - PLL Enabled List of Tables Copyright © 2003–2012, Texas Instruments Incorporated...
  • Page 7 F280x Thermal Model 100-pin PZ Results ................C280x Thermal Model 100-pin GGM Results .................. C280x Thermal Model 100-pin PZ Results ................F2809 Thermal Model 100-pin GGM Results ................. F2809 Thermal Model 100-pin PZ Results List of Tables Copyright © 2003–2012, Texas Instruments Incorporated...

  • Page 8: F280X, F2801X, C280X Dsps

    Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TMS320C28x, Code Composer Studio, DSP/BIOS, MicroStar BGA, C28x, TI, TMS320C2000 are trademarks of Texas Instruments.

  • Page 9: Getting Started

    For more application software and other advanced topics, visit the TI™ website at http://www.ti.com or http://www.ti.com/c2000getstarted. F280x, F2801x, C280x DSPs Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 10: Introduction

    F2809, F2808, F2806, F2802, F2801, C2802, C2801, F28015, and F28016, respectively. TMS320F28015 and TMS320F28016 are abbreviated as F2801x. Table 2-1 provides a summary of features for each device. Introduction Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 11: Hardware Features (100-Mhz Devices)

    (2) See Section 5.1, Device and Development Support Tool Nomenclature, for descriptions of device stages. Introduction Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 12: Hardware Features (60-Mhz Devices)

    (2) See Section 5.1, Device and Development Support Tool Nomenclature, for descriptions of device stages. Introduction Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 13: Pin Assignments

    DD3VFL TEST1 ADCINB2 TEST2 ADCINB1 GPIO26/ECAP3/EQEP2I/SPICLKB ADCINB0 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO DDAIO Figure 2-1. TMS320F2809, TMS320F2808 100-Pin PZ LQFP (Top View) Introduction Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 14: Tms320F2809, Tms320F2808 100-Pin Pz Lqfp (Top View)

    ADCINB3 DD3VFL TEST1 ADCINB2 TEST2 ADCINB1 GPIO26/ECAP3/EQEP2I/SPICLKB ADCINB0 GPIO32/SDAA/EPWMSYNCI/ADCSOCAO DDAIO Figure 2-2. TMS320F2806 100-Pin PZ LQFP (Top View) Introduction Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 15: Tms320F2806 100-Pin Pz Lqfp (Top View)

    On the C280x devices, the V pin is V DD3VFL DDIO Figure 2-3. TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801 100-Pin PZ LQFP (Top View) Introduction Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 16: Tms320F2802, Tms320F2801, Tms320C2802, Tms320C2801 100-Pin Pz Lqfp (Top View)

    CANTXA (pin 7) and CANRXA (pin 6) pins are not applicable for the TMS320F28015. Figure 2-4. TMS320F2801x 100-Pin PZ LQFP (Top View) Introduction Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 17: Tms320F2801X 100-Pin Pz Lqfp (Top View)

    Figure 2-5. TMS320F2809, TMS320F2808, TMS320F2806,TMS320F2802, TMS320F2801, TMS320F28016, TMS320F28015, TMS320C2802, TMS320C2801 100-Ball GGM and ZGM MicroStar BGA™ (Bottom View) Introduction Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 18: Signal Descriptions

    X1 pin), tie the XCLKIN pin to GND. (I) (1) I = Input, O = Output, Z = High impedance, OD = Open drain, ↑ = Pullup, ↓ = Pulldown Introduction Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s):...
  • Page 19 NOTE: Use the ADC Clock rate to derive the ESR specification from the capacitor data sheet that is used in the system. Introduction Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...
  • Page 20 The peripheral signals that are listed under them are alternate functions. (3) The pullups on GPIO0-GPIO11 pins are not enabled at reset. Introduction Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...
  • Page 21 Trip zone input 5 (I) (1) The pullups on GPIO0-GPIO11 pins are not enabled at reset. (2) The pullups on GPIO12-GPIO34 are enabled upon reset. Introduction Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...
  • Page 22 SCI transmit data (O) Trip zone 6 input (I) (1) The pullups on GPIO12-GPIO34 are enabled upon reset. Introduction Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...
  • Page 23 (1) The pullups on GPIO12-GPIO34 are enabled upon reset. NOTE Some peripheral functions may not be available in TMS320F2801x devices. See Table 2-2 for details. Introduction Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 24: Functional Overview

    The 1K x 16 OTP has been replaced with 1K x 16 ROM for C280x devices. Figure 3-1. Functional Block Diagram Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 25: Memory Maps

    Protected means the order of Write followed by Read operations is preserved rather than the pipeline order. Certain memory ranges are EALLOW protected against spurious writes after configuration. Figure 3-2. F2809 Memory Map Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 26: F2809 Memory Map

    Protected means the order of Write followed by Read operations is preserved rather than the pipeline order. Certain memory ranges are EALLOW protected against spurious writes after configuration. Figure 3-3. F2808 Memory Map Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 27: F2808 Memory Map

    Protected means the order of Write followed by Read operations is preserved rather than the pipeline order. Certain memory ranges are EALLOW protected against spurious writes after configuration. Figure 3-4. F2806 Memory Map Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 28: F2806 Memory Map

    Some locations in ROM are reserved for TI. See Table 3-5 for more information. Figure 3-5. F2802, C2802 Memory Map Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 29: F2802, C2802 Memory Map

    Some locations in ROM are reserved for TI. See Table 3-5 for more information. Figure 3-6. F2801, F28015, F28016, C2801 Memory Map Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 30: Addresses Of Flash Sectors In F2809

    (program branch instruction here) Security Password (128-Bit) 0x3F 7FF8 – 0x3F 7FFF (Do not program to all zeros) Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 31: Addresses Of Flash Sectors In F2801, F28015, F28016

    (the penalty is extra cycles are added to align the operations). This mode is programmable and by default, it will protect the selected zones. Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s):...

  • Page 32: Wait-States

    0-wait minimum locations are hardwired for 16 wait-states. See Section 3.2.5 for more information. H0 SARAM 0-wait Fixed Boot-ROM 1-wait Fixed Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 33: Brief Descriptions

    3.2.3 Peripheral Bus To enable migration of peripherals between various Texas Instruments (TI) DSP family of devices, the 280x devices adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes the various busses that make up the processor Memory Bus into a single bus consisting of 16 address lines and 16 or 32 data lines and associated control signals.

  • Page 34: Real-Time Jtag And Analysis

    The partitioning is performed within the linker. The C28x device presents a unified memory map to the programmer. This makes for easier programming in high-level languages. Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 35: L0, L1, H0 Sarams

    Boot to OTP Jump to OTP address 0x3D 7800 Parallel I/O Boot Load data from GPIO0 - GPIO15 Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 36: Security

    THE CODE SECURITY MODULE (CSM) INCLUDED ON THIS DEVICE WAS DESIGNED TO PASSWORD PROTECT THE DATA STORED IN THE ASSOCIATED MEMORY (EITHER ROM OR FLASH) AND IS WARRANTED BY TEXAS INSTRUMENTS (TI), IN ACCORDANCE WITH ITS STANDARD TERMS AND CONDITIONS, TO CONFORM TO TI'S PUBLISHED SPECIFICATIONS FOR THE WARRANTY PERIOD APPLICABLE FOR THIS DEVICE.

  • Page 37: Peripheral Interrupt Expansion (Pie) Block

    A reset or external signal can wake the device from this mode. Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 38: Peripheral Frames 0, 1, 2 (Pfn)

    The enhanced capture peripheral uses a 32-bit time base and registers up to four programmable events in continuous/one-shot capture modes. This peripheral can also be configured to generate an auxiliary PWM signal. Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 39: Serial Port Peripherals

    3-9. Peripheral These are peripherals that are mapped to the 16-bit peripheral bus. Frame 2: Table 3-10. Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 40: Peripheral Frame 0 Registers

    (1) The eCAN control registers only support 32-bit read/write operations. All 32-bit accesses are aligned to even address boundaries. (2) Missing segments of memory space are reserved and should not be used in applications. Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s):...

  • Page 41: Device Emulation Registers

    The PIE vector table does not, however, include a reset vector. Therefore, TRAP #0 should not be used when the PIE is enabled. Doing so will result in undefined behavior. Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s):...
  • Page 42 GPIO0.int nmi_select XNMI_XINT13 GPIO Interrupt Control XNMICR(15:0) GPIO31.int XNMICTR(15:0) GPIOXNMISEL(4:0) Figure 3-7. External and PIE Interrupt Sources Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 43: External And Pie Interrupt Sources

    1) No peripheral within the group is asserting interrupts. 2) No peripheral interrupts are assigned to the group (example PIE group 12). Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 44: External Interrupts

    XINT1 counter register XINT2CTR 0x7079 XINT2 counter register Reserved 0x707A – 0x707E Reserved XNMICTR 0x707F XNMI counter register Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 45: System Control

    CLKIN is the clock into the CPU. It is passed out of the CPU as SYSCLKOUT (that is, CLKIN is the same frequency as SYSCLKOUT). Figure 3-9. Clock and Reset Domains Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 46: Osc And Pll Block

    2. A 1.8-V external oscillator can be directly connected to the X1 pin. The X2 pin should be left unconnected and the XCLKIN pin tied low. The logic-high level in this case should not exceed V Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s):...

  • Page 47: External Reference Oscillator Clock Option

    The vendor can also advise the customer regarding the proper tank component values that will produce proper start up and stability over the entire operating range. Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s):...

  • Page 48: Pll-Based Clock Module

    External clock source operation - This mode allows the internal oscillator to be bypassed. The device clocks are generated from an external clock source input on the X1 or the XCLKIN pin. Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s):...

  • Page 49: Loss Of Input Clock

    Such a circuit would also help in detecting failure of the flash memory and the V rail. DD3VFL Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 50: Watchdog Block

    In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so is the WATCHDOG. Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 51: Low-Power Modes Block

    IDLE instruction was executed. See the TMS320x280x, 2801x, 2804x DSP System Control and Interrupts Reference Guide (literature number SPRU712) for more details. Functional Overview Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 52: Peripherals

    16-Bit Prescale Counter SYSCLKOUT PSCH:PSC TCR.4 32-Bit Counter (Timer Start Status) Borrow TIMH:TIM Borrow TINT Figure 4-1. CPU-Timers Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 53: Cpu-Timer Interrupt Signals And Output Signal

    0x0C12 CPU-Timer 2, Period Register TIMER2PRDH 0x0C13 CPU-Timer 2, Period Register High TIMER2TCR 0x0C14 CPU-Timer 2, Control Register Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 54: Enhanced Pwm Modules (Epwm1/2/3/4/5/6)

    Figure 4-3. Multiple PWM Modules in a 280x System Table 4-2 shows the complete ePWM register set per module. Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 55: Epwm Control And Status Registers

    0x6960 1 / 0 HRPWM Configuration Register (1) Registers that are EALLOW protected. (2) Applicable to F2809 only Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 56: Epwm Sub-Modules Showing Critical Internal Signal Interconnections

    CMPB Shadow (16) CTR = ZERO TZ1 to TZ6 Figure 4-4. ePWM Sub-Modules Showing Critical Internal Signal Interconnections Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 57: Hi-Resolution Pwm (Hrpwm)

    Upon reset, ECAP1ENCLK, ECAP2ENCLK, ECAP3ENCLK, and ECAP4ENCLK are set to low, indicating that the peripheral clock is off. Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 58: Ecap Functional Block Diagram

    Continuous/ Trigger One-Shot to PIE CTR_OVF Capture Control Flag CTR=PRD Control CTR=CMP Figure 4-5. eCAP Functional Block Diagram Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 59: Ecap Control And Status Registers

    Capture Interrupt Force Register Reserved 0x6A1A – 0x6A3A – 0x6A5A – 0x6A7A – Reserved 0x6A1F 0x6A3F 0x6A5F 0x6A7F Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 60: Enhanced Qep Modules (Eqep1/2)

    QPOSCNT QEINT QPOSCMP QPOSINIT QFRC QPOSMAX QCLR QPOSCTL Enhanced QEP (eQEP) Peripheral Figure 4-6. eQEP Functional Block Diagram Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 61: Eqep Control And Status Registers

    Capture Timer Latch QCPRDLAT 0x6B20 0x6B60 eQEP Capture Period Latch Reserved 0x6B21– 0x6B61 – 31/0 Reserved 0x6B3F 0x6B7F Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 62: Enhanced Analog-To-Digital Converter (Adc) Module

    RESULT register. Autosequencing allows the system to convert the same channel multiple times, allowing the user to perform oversampling algorithms. This gives increased resolution over traditional single- sampled conversion results. Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 63: Block Diagram Of The Adc Module

    ADC module goes into low-power mode. This mode also will stop the clock to the CPU, which will stop the HSPCLK; therefore, the ADC register logic will be turned off indirectly. Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 64: Adc Pin Connections With Internal Reference

    Analog inputs must be driven from an operational amplifier that does not degrade the ADC performance. Figure 4-8. ADC Pin Connections With Internal Reference Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 65: Adc Connections If The Adc Is Not Used

    When the ADC module is used in an application, unused ADC input pins should be connected to analog ground (V SS1AGND SS2AGND Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 66: Adc Registers

    Locations in Peripheral frame 0 space (0x0B00-0x0B0F) are 0 wait sates and right justified. During high-speed/continuous conversion use of the ADC, use the 0 wait-state locations for fast transfer of ADC results to user memory. Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s):...

  • Page 67: Enhanced Controller Area Network (Ecan) Modules (Ecan-A And Ecan-B)

    For a SYSCLKOUT of 100 MHz, the smallest bit rate possible is 15.625 kbps. For a SYSCLKOUT of 60 MHz, the smallest bit rate possible is 9.375 kbps. Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s):...

  • Page 68: Ecan Block Diagram And Interface Circuit

    Standby & Sleep Adjustable None – –40°C to 125°C SN65HVD235 3.3 V Standby Adjustable None Autobaud –40°C to 125°C Loopback Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 69: Ecan-A Memory Map

    If the eCAN module is not used in an application, the RAM available (LAM, MOTS, MOTO, and mailbox RAM) can be used as general-purpose RAM. The CAN module clock should be enabled for this. Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 70: Ecan-B Memory Map

    63EAh-63EBh Message Data Low - MDL 63ECh-63EDh Message Data High - MDH 63EEh-63EFh Figure 4-12. eCAN-B Memory Map Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 71: Can Register Map

    CANTOS 0x6032 0x6232 Time-out status (Reserved in SCC mode) (1) These registers are mapped to Peripheral Frame 1. Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 72: Serial Communications Interface (Sci) Modules (Sci-A, Sci-B)

    When a register is accessed, the register data is in the lower byte (7–0), and the upper byte (15–8) is read as zeros. Writing to the upper byte has no effect. Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s):...

  • Page 73: Sci-A Registers

    (1) Registers in this table are mapped to peripheral bus 16 space. This space only allows 16-bit accesses. 32-bit accesses produce undefined results. (2) These registers are new registers for the FIFO mode. Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 74: Serial Communications Interface (Sci) Module Block Diagram

    RX ERR INT ENA SCI RX Interrupt Select Logic SCICTL1.6 Figure 4-13. Serial Communications Interface (SCI) Module Block Diagram Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 75: Serial Peripheral Interface (Spi) Modules (Spi-A, Spi-B, Spi-C, Spi-D)

    (15–8) is read as zeros. Writing to the upper byte has no effect. Enhanced feature: • 16-level transmit/receive FIFO • Delayed transmit control Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 76: Spi-A Registers

    (1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined results. Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 77: Spi-C Registers

    (1) Registers in this table are mapped to Peripheral Frame 2. This space only allows 16-bit accesses. 32-bit accesses produce undefined results. Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 78: Spi Module Block Diagram (Slave Mode)

    SPICLK SPISTE is driven low by the master for a slave device. Figure 4-14. SPI Module Block Diagram (Slave Mode) Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 79: Inter-Integrated Circuit (I2C)

    An additional interrupt that can be used by the CPU when in FIFO mode • Module enable/disable capability • Free data format mode Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 80: I2C Peripheral Module Interfaces

    I2C receive shift register (not accessible to the CPU) I2CXSR I2C transmit shift register (not accessible to the CPU) Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 81: Gpio Mux

    GPIO pin selected. GPxDAT latch/read are accessed at the same memory location. Figure 4-16. GPIO MUX Block Diagram Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 82: Gpio Registers

    0x6FE3 – Reserved Reserved 0x6FE7 GPIOLPMSEL 0x6FE8 LPM GPIO Select Register (GPIO0 to 31) 0x6FEA – Reserved Reserved 0x6FFF Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 83: F2808 Gpio Mux Table

    (4) The word "Reserved" means that there is no peripheral assigned to this GPxMUX1/2 register setting. Should it be selected, the state of the pin will be undefined and the pin may be driven. This selection is a reserved configuration for future expansion. Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s):...

  • Page 84: Qualification Using Sampling Window

    GPIO pin. Also, when an input signal is not selected, the input signal will default to either a 0 or 1 state, depending on the peripheral. Peripherals Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s):...

  • Page 85: Device Support

    SPRS230N – OCTOBER 2003 – REVISED MAY 2012 Device Support Texas Instruments (TI) offers an extensive line of development tools for the C28x™ generation of DSPs, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules.

  • Page 86: Example Of Tms320X280X/2801X Device Nomenclature

    Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used.

  • Page 87: Documentation Support

    TMS320x280x, 2801x, 2804x DSP System Control and Interrupts Reference Guide describes the various interrupts and system control features of the 280x digital signal processors (DSPs). Device Support Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...
  • Page 88 C28x™ core. SPRU625 TMS320C28x DSP/BIOS 5.32 Application Programming Interface (API) Reference Guide describes development using DSP/BIOS. Device Support Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...
  • Page 89 (BPSK) with a Single DSP Controller presents a complete implementation of a power line modem following CEA-709 protocol using a single DSP. Device Support Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...
  • Page 90 C compiler to assist with C-callable assembly routines. SPRAA58 TMS320x281x to TMS320x280x Migration Overview describes differences between the Texas Instruments TMS320x281x and the TMS320x280x/2801x/2804x DSPs to assist in application migration. Software SPRC191 C280x, C2801x C/C++ Header Files and Peripheral Examples...
  • Page 91 For questions and support, contact the Product Information Center listed at the http://www.ti.com/sc/docs/pic/home.htm site. Device Support Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 92: Community Resources

    TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices.

  • Page 93: Electrical Specifications

    For additional information, see IC Package Thermal Metrics Application Report (literature number SPRA953) and Reliability Data for TMS320LF24xx and TMS320F28xx Devices Application Report (literature number SPRA963). Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s):...

  • Page 94: Recommended Operating Conditions

    DDIO DDIO enabled Output current, pullup or or 0 V ±2 μA DDIO pulldown disabled Input capacitance Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 95: Current Consumption

    If this is done, the current drawn by the device will be more than the numbers specified in the current consumption tables. Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 96: Tms320F2806 Current Consumption By Power-Supply Pins At 100-Mhz Sysclkout

    If this is done, the current drawn by the device will be more than the numbers specified in the current consumption tables. Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 97: Tms320F2802, Tms320F2801 Current Consumption By Power-Supply Pins At 100-Mhz Sysclkout

    If this is done, the current drawn by the device will be more than the numbers specified in the current consumption tables. Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 98: Tms320C2802, Tms320C2801 Current Consumption By Power-Supply Pins At 100-Mhz Sysclkout

    If this is done, the current drawn by the device will be more than the numbers specified in the current consumption tables. Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 99: Reducing Current Consumption

    (enabled by that application) must be added to the baseline I current. Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 100: Current Consumption Graphs

    60 MHz. For example, to compute the current of F2801-60 device, the contribution by the following peripherals must be subtracted from I : ePWM4/5/6, eCAP3/4, eQEP2, SCI-B. Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 101: Typical Operational Current Versus Frequency (C280X)

    Device Power Vs SYSCLKOUT 400.0 300.0 200.0 100.0 SYSCLKOUT (MHz) TOTAL POWER Figure 6-4. Typical Operational Power Versus Frequency (C280x) Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 102: Emulator Connection Without Signal Buffering For The Dsp

    EMU1 EMU1 TRST TRST TCK_RET JTAG Header Figure 6-5. Emulator Connection Without Signal Buffering for the DSP Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 103: Timing Parameter Symbology

    (2 ns or longer) from the data sheet timing. Figure 6-6. 3.3-V Test Load Circuit Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 104: Device Clock Table

    (2) Lower LSPCLK and HSPCLK will reduce device power consumption. (3) This is the default reset value if SYSCLKOUT = 60 MHz. Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 105: Clock Requirements And Characteristics

    (2) H = 0.5t c(XCO) (3) OSCCLK is either the output of the on-chip oscillator or the output from an external oscillator. Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 106: Power Sequencing

    High V 1.2-A dc/dc converter in 4x4 QFN package Texas Instruments DC/DC TPS6230x 500-mA converter in WCSP package Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 107: Power-On Reset

    Section 6.8 for requirements to ensure a high-impedance state for GPIO pins during power-up. Figure 6-8. Power-on Reset Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 108: Warm Reset

    Boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or without PLL enabled. Figure 6-9. Warm Reset Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 109: General-Purpose Input/Output (Gpio)

    Fall time, GPIO switching high to low All GPIOs f(GPO) Toggling frequency, GPO pins fGPO GPIO r(GPO) f(GPO) Figure 6-11. General-Purpose Output Timing Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 110: Gpio - Input Timing

    V for an active low signal and V to V for an active high signal. w(GPI) Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 111: Sampling Window Width For Input Signals

    Figure 6-13. General-Purpose Input Timing NOTE The pulse-width requirement for general-purpose input is applicable for the XINT2_ADCSOC signal as well. Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 112: Low-Power Mode Wakeup Timing

    WAKE INT WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS. Figure 6-14. IDLE Entry and Exit Timing Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 113: Standby Entry And Exit Timing Diagram

    Normal execution resumes. The device will respond to the interrupt (if enabled). Figure 6-15. STANDBY Entry and Exit Timing Diagram Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 114: Halt Wake-Up Using Gpion

    Clocks to the core and peripherals are enabled. The HALT mode is now exited. The device will respond to the interrupt (if enabled), after a latency. Normal operation resumes. Figure 6-16. HALT Wake-Up Using GPIOn Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 115: Enhanced Control Peripherals

    With input qualifier cycles c(SCO) w(IQSW) (1) For an explanation of the input qualifier parameters, see Table 6-15. Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 116: High-Resolution Pwm Characteristics At Sysclkout = 60-100 Mhz

    Delay time, external clock to counter increment cycles d(CNTR)xin c(SCO) Delay time, QEP input edge to position compare sync output cycles d(PCS-OUT)QEP c(SCO) Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 117: External Interrupt Timing

    + 12t cycles d(INT) w(IQSW) c(SCO) (1) For an explanation of the input qualifier parameters, see Table 6-15. Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 118: I2C Electrical Specification And Timing

    Table 6-35 lists the timing (clock phase = 1). Figure 6-20 Figure 6-21 show the timing waveforms. Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 119: Spi Master Mode External Timing (Clock Phase = 0)

    Slave mode transmit 12.5-MAX, slave mode receive 12.5-MHz MAX. (5) The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6). Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s):...

  • Page 120: Spi Master Mode External Timing (Clock Phase = 0)

    (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes. Figure 6-20. SPI Master Mode External Timing (Clock Phase = 0) Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s):...

  • Page 121: Spi Master Mode External Timing (Clock Phase = 1)

    = LSPCLK cycle time c(LCO) (5) The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6). Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 122: Spi Master Mode External Timing (Clock Phase = 1)

    (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes. Figure 6-21. SPI Master Mode External Timing (Clock Phase = 1) Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s):...

  • Page 123: Spi Slave Mode Timing

    (SPICLK) of the last data bit. c(SPC) Figure 6-22. SPI Slave Mode External Timing (Clock Phase = 0) Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 124: Spi Slave Mode External Timing (Clock Phase = 0)

    (SPICLK) of the last data bit. c(SPC) Figure 6-23. SPI Slave Mode External Timing (Clock Phase = 1) Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 125: On-Chip Analog-To-Digital Converter

    To avoid this, the analog inputs should be kept within these limits. (7) TI recommends using high precision external reference TI part REF3020/3120 or equivalent for 2.048-V reference. Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s):...

  • Page 126: Adc Power-Up Control Bit Timing

    V and V includes current into V and V DDA18 DD1A18 DD2A18 DDA3.3 DDA2 DDAIO Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 127: Definitions

    The conversion can be performed in two different conversion modes: • Sequential sampling mode (SMODE = 0) • Simultaneous sampling mode (SMODE = 1) Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 128: Sequential Sampling Mode (Single-Channel) (Smode = 0)

    Delay time for successive results to (2 + Acqps) * 160 ns d(schx_n+1) appear in Result register c(ADCCLK) Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 129: Simultaneous Sampling Mode (Dual-Channel) (Smode = 1)

    Delay time for successive results (3 + Acqps) * t 240 ns d(schB0_n+1 ) c(ADCCLK) to appear in Result register Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 130: Detailed Descriptions

    Spurious Free Dynamic Range (SFDR) SFDR is the difference in dB between the rms amplitude of the input signal and the peak spurious signal. Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 131: Flash Timing

    However, the erase operation is needed on all subsequent programming operations. Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 132: Flash/Otp Access Timing

    WAIT-STATE WAIT-STATE 13.33 16.67 33.33 66.67 (1) Random wait-state must be greater than or equal to 1. Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 133: Rom Timing (C280X Only)

    (ns) STATE STATE 13.33 33.33 66.67 (1) Random wait-state must be greater than or equal to 1. Electrical Specifications Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 134: Migrating From F280X Devices To C280X Devices

    For errata applicable to 280x devices, see the TMS320F280x, TMS320C280x, and TMS320F2801x DSC Silicon Errata (literature number SPRZ171). Migrating From F280x Devices to C280x Devices Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 135: Revision History

    Flash Parameters at 100-MHz SYSCLKOUT: • Added footnote about flash memory being in an erased state when the device is shipped Revision History Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802...

  • Page 136: Mechanical Data

    [°C/W] High k PCB 28.15 26.89 25.68 24.22 Ψ [°C/W] 0.38 0.35 0.33 0.44 θ 10.36 θ 13.3 Mechanical Data Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...

  • Page 137: F2809 Thermal Model 100-Pin Pz Results

    θ [°C/W] High k PCB 44.02 28.34 36.28 33.68 Ψ [°C/W] 0.56 0.95 θ 7.06 θ 28.76 Mechanical Data Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802 TMS320C2801 TMS320F28016 TMS320F28015...
  • Page 138 PACKAGE OPTION ADDENDUM www.ti.com 24-Sep-2012 PACKAGING INFORMATION Orderable Device Package Type Package Pins Package Qty Lead/ Samples Status Eco Plan MSL Peak Temp Drawing Ball Finish (Requires Login) TMS320C2801GGMA ACTIVE Call TI Call TI MICROSTAR TMS320C2801GGMS ACTIVE Call TI Call TI MICROSTAR TMS320C2801PZA ACTIVE...
  • Page 139 PACKAGE OPTION ADDENDUM www.ti.com 24-Sep-2012 Orderable Device Package Type Package Pins Package Qty Lead/ Samples Status Eco Plan MSL Peak Temp Drawing Ball Finish (Requires Login) TMS320F28016PZQ ACTIVE LQFP Green (RoHS CU NIPDAU Level-2-260C-1 YEAR & no Sb/Br) TMS320F28016PZS ACTIVE LQFP Green (RoHS CU NIPDAU Level-2-260C-1 YEAR...
  • Page 140 PACKAGE OPTION ADDENDUM www.ti.com 24-Sep-2012 Orderable Device Package Type Package Pins Package Qty Lead/ Samples Status Eco Plan MSL Peak Temp Drawing Ball Finish (Requires Login) TMS320F2802ZGMA ACTIVE Green (RoHS SNAGCU Level-3-260C-168 HR MICROSTAR & no Sb/Br) TMS320F2802ZGMS ACTIVE Green (RoHS SNAGCU Level-3-260C-168 HR MICROSTAR...
  • Page 141 PACKAGE OPTION ADDENDUM www.ti.com 24-Sep-2012 Orderable Device Package Type Package Pins Package Qty Lead/ Samples Status Eco Plan MSL Peak Temp Drawing Ball Finish (Requires Login) TMS320F2809PZA ACTIVE LQFP Green (RoHS CU NIPDAU Level-2-260C-1 YEAR & no Sb/Br) TMS320F2809PZQ ACTIVE LQFP Green (RoHS CU NIPDAU Level-2-260C-1 YEAR...
  • Page 142 PACKAGE OPTION ADDENDUM www.ti.com 24-Sep-2012 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
  • Page 143 MECHANICAL DATA MPBG028B FEBRUARY 1997 – REVISED MAY 2002 GGM (S–PBGA–N100) PLASTIC BALL GRID ARRAY 10,10 7,20 TYP 9,90 0,80 0,40 A1 Corner Bottom View 0,95 0,85 1,40 MAX Seating Plane 0,55 0,10 0,08 0,45 0,45 0,35 4145257–3/C 12/01 NOTES: A. All linear dimensions are in millimeters.
  • Page 145 MECHANICAL DATA MTQF013A – OCTOBER 1994 – REVISED DECEMBER 1996 PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK 0,27 0,50 0,08 0,17 0,13 NOM 12,00 TYP Gage Plane 14,20 13,80 0,25 16,20 0,05 MIN 0 – 7 15,80 1,45 0,75 1,35 0,45 Seating Plane 0,08 1,60 MAX 4040149 /B 11/96...
  • Page 147 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue.

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