Multichannel Audio Serial Ports (Mcasp0, Mcasp1, And Mcasp2) - Texas Instruments TMS320C6722 User Manual

TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
4.13

Multichannel Audio Serial Ports (McASP0, McASP1, and McASP2)

The McASP serial port is specifically designed for multichannel audio applications. Its key features are:
Flexible clock and frame sync generation logic and on-chip dividers
Up to sixteen transmit or receive data pins and serializers
Large number of serial data format options, including:
– TDM Frames with 2 to 32 time slots per frame (periodic) or 1 slot per frame (burst).
– Time slots of 8,12,16, 20, 24, 28, and 32 bits.
– First bit delay 0, 1, or 2 clocks.
– MSB or LSB first bit order.
– Left- or right-aligned data words within time slots
DIT Mode (optional) with 384-bit Channel Status and 384-bit User Data registers.
Extensive error-checking and mute generation logic
All unused pins GPIO-capable
Peripheral
Configuration
Bus
DIT RAM
Optional
Transmit
Formatter
McASP
DMA Bus
(Dedicated)
Receive
Formatter
68 Peripheral and Electrical Specifications
Receive Logic
GIO
Clock/Frame Generator
Control
State Machine
Clock Check and
Error Detection
384 C
384 U
Transmit Logic
Clock/Frame Generator
State Machine
Serializer 0
Serializer 1
Serializer y
McASPx (x = 0, 1, 2)
Figure 4-25. McASP Block Diagram
Pins Function
AHCLKRx Receive Master Clock
ACLKRx Receive Bit Clock
AFSRx Receive Left/Right Clock or Frame Sync
AMUTEINx The McASPs DO NOT have
dedicated AMUTEINx pins.
AMUTEx
AFSXx
Transmit Left/Right Clock or Frame Sync
ACLKXx Transmit Bit Clock
Transmit Master Clock
AHCLKXx
AXRx[0] Transmit/Receive Serial Data Pin
AXRx[1] Transmit/Receive Serial Data Pin
AXRx[y] Transmit/Receive Serial Data Pin
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