Texas Instruments TMS320C6722 User Manual page 88

TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
NO.
Required delay from SPIx_SCS asserted at slave to first
25 t
d(SCSL_SPC)S
SPIx_CLK edge at slave.
Required delay from final
26 t SPIx_CLK edge before
d(SPC_SCSH)S
SPIx_SCS is deasserted.
Delay from master asserting SPIx_SCS to slave driving
27 t
ena(SCSL_SOMI)S
SPIx_SOMI valid
Delay from master deasserting SPIx_SCS to slave 3-stating
28 t
dis(SCSH_SOMI)S
SPIx_SOMI
Delay from master deasserting SPIx_SCS to slave driving
29 t
ena(SCSL_ENA)S
SPIx_ENA valid
Delay from final clock receive
edge on SPIx_CLK to slave
30 t
dis(SPC_ENA)S
3-stating or driving high
SPIx_ENA.
(1) These parameters are in addition to the general timings for SPI slave modes
(2) P = SYSCLK2 period
(3) Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four slave clocking modes.
(4) SPIx_ENA is driven low after the transmission completes if the SPIINT0.ENABLE_HIGHZ bit is programmed to 0. Otherwise it is
3-stated. If 3-stated, an external pullup resistor should be used to provide a valid level to the master. This option is useful when tying
several SPI slave devices to a single master.
88 Peripheral and Electrical Specifications
(1)
Table 4-32. Additional
Polarity = 0, Phase = 0,
from SPIx_CLK falling
Polarity = 0, Phase = 1,
from SPIx_CLK falling
Polarity = 1, Phase = 0,
from SPIx_CLK rising
Polarity = 1, Phase = 1,
from SPIx_CLK rising
Polarity = 0, Phase = 0,
from SPIx_CLK falling
Polarity = 0, Phase = 1,
from SPIx_CLK rising
Polarity = 1, Phase = 0,
(4)
from SPIx_CLK rising
Polarity = 1, Phase = 1,
from SPIx_CLK falling
SPI Slave Timings, 5-Pin Option
(Table 4-26).
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(2) (3)
MIN MAX
P
0.5t + P + 10
c(SPC)M
P + 10
0.5t + P + 10
c(SPC)M
P + 10
P + 10
P + 10
2P + 15
2P + 15
2P + 15
2P + 15
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UNIT
ns
ns
ns
ns
15 ns
ns