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2.9 Pin Assignments
2.9.1 Pin Maps
Figure 2-8
and
Figure 2-9
144-pin RFP package, respectively.
T
V
DV
EM_WE
SS
DD
EM_D[23]
R
DV
/UHPI_
EM_CAS
DD
HA[7]
EM_D[21]
EM_D[20]
UHPI_
P
TCK
/UHPI_
HD[24]
HA[5]
EM_D[22]
UHPI_
UHPI_
N
EMU[1]
HD[25]
HD[26]
UHPI_
M
EMU[0]
TDO
HD[27]
UHPI_
UHPI_
L
TDI
HD[28]
HD[30]
K
V
PLLHV
TMS
SS
J
OSCV
OSCIN
OSCOUT
SS
UHPI_
H
HD[16]
CLKIN
V
SS
/HHWIL
UHPI_
G
V
RESET
SS
HD[17]
UHPI_
F
AFSR1
AFSX1
HD[19]
UHPI_
E
ACLKR1
ACLKX1
HD[21]
UHPI_
D
AHCLKX1
AMUTE1
HD[22]
AHCLKX0
UHPI_
C
AMUTE0
/AHCLKX2
HD[23]
UHPI_
AHCLKR0
B
DV
DD
HBE[3]
/AHCLKR1
A
V
DV
AFSX0
SS
DD
1
2
3
Figure 2-8. 256-Terminal Ball Grid Array (GDH/ZDH Suffix)—Bottom View
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show the pin assignments on the 256-terminal GDH/ZDH package and the
EM_D[7]
EM_D[5]
EM_D[3]
V
SS
EM_WE_
EM_D[6]
EM_D[4]
EM_D[2]
DQM[0]
EM_D[19]
EM_D[17]
EM_D[31]
/UHPI_
/UHPI_
/UHPI_
/UHPI_
HA[4]
HA[3]
HA[1]
HA[15]
EM_D[18]
EM_D[16]
/UHPI_
DV
/UHPI_
/UHPI_
DD
HA[6]
HA[2]
HA[0]
DV
V
CV
CV
DD
SS
DD
DD
UHPI_
V
V
V
SS
SS
SS
HD[29]
TRST
CV
V
V
DD
SS
SS
OSCV
CV
V
V
DD
DD
SS
SS
UHPI_
CV
V
V
DD
SS
SS
HD[31]
UHPI_
CV
V
V
DD
SS
SS
HD[18]
UHPI_
V
V
V
SS
SS
SS
HD[20]
DV
V
CV
CV
DD
SS
DD
DD
UHPI_
UHPI_
DV
DV
DD
DD
HRDY
HDS[1]
UHPI_
UHPI_
UHPI_
UHPI_
HBE[1]
HBE[0]
HBE[2]
HDS[2]
AXR0[15]
AXR0[13]
AXR0[12]
AFSR0
/AXR2[0]
/AXR1[0]
/AXR1[1]
AXR0[14]
ACLKX0
ACLKR0
V
SS
/AXR2[1]
4
5
6
7
TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
EM_D[0]
EM_D[14]
V
EM_D[11]
SS
EM_D[1]
EM_D[15]
EM_D[13]
EM_D[12]
EM_D[28]
EM_D[26]
EM_D[24]
DV
/UHPI_
/UHPI_
/UHPI_
DD
HA[12]
HA[10]
HA[8]
EM_D[30]
EM_D[29]
EM_D[27]
EM_D[25]
/UHPI_
/UHPI_
/UHPI_
/UHPI_
HA[14]
HA[13]
HA[11]
HA[9]
CV
CV
CV
CV
DD
DD
DD
DD
V
V
V
V
SS
SS
SS
SS
V
V
V
V
SS
SS
SS
SS
V
V
V
V
SS
SS
SS
SS
V
V
V
V
SS
SS
SS
SS
V
V
V
V
SS
SS
SS
SS
V
V
V
V
SS
SS
SS
SS
CV
CV
CV
CV
DD
DD
DD
DD
UHPI_
UHPI_
AMUTE2/
ACLKX2
HRW
HCNTL[0]
HINT
UHPI_
UHPI_
UHPI_
AFSX2
HCS
HAS
HCNTL[1]
AXR0[8]
AXR0[7]
AXR0[5]
AXR0[10]
/AXR1[5]
/SPI1_
/SPI1_
/SPI1_
/AXR1[3]
CLK
SCS
SOMI
AXR0[9]
AXR0[6]
AXR0[11]
/AXR1[4]
V
/SPI1_
SS
/SPI1_
/AXR1[2]
ENA
SIMO
8
9
10
11
SPRS268E – MAY 2005 – REVISED JANUARY 2007
EM_WE_
EM_D[9]
EM_CKE
DV
DQM[1]
EM_WE_
EM_D[10]
EM_D[8]
EM_CLK
DQM[3]
EM_WE_
UHPI_
EM_A[12]
EM_A[11]
DQM[2]
HD[7]
UHPI_
UHPI_
DV
EM_A[8]
DD
HD[5]
HD[6]
UHPI_
V
DV
EM_A[6]
SS
DD
HD[2]
UHPI_
UHPI_
V
EM_A[4]
SS
HD[3]
HD[4]
UHPI_
UHPI_
CV
EM_A[2]
DD
HD[0]
HD[1]
UHPI_
CV
DV
EM_A[1]
DD
DD
HD[15]
UHPI_
UHPI_
CV
EM_A[10]
DD
HD[14]
HD[13]
UHPI_
UHPI_
CV
EM_BA[0]
DD
HD[12]
HD[11]
UHPI_
UHPI_
V
EM_CS[0]
SS
HD[10]
HD[9]
UHPI_
V
DV
EM_CS[2]
SS
DD
HD[8]
DV
DV
EM_WAIT
EM_OE
DD
DD
SPI0_SCS
AFSR2
ACLKR2
AHCLKR2
/I2C1_
SPI0_
SPI0_
SOMI
AXR0[3]
AXR0[1]
/I2C0_
SIMO
SDA
AXR0[4]
AXR0[2]
AXR0[0]
DV
12
13
14
Device Overview
V
DD
SS
DV
DD
EM_A[9]
EM_A[7]
EM_A[5]
EM_A[3]
V
SS
EM_A[0]
EM_BA[1]
V
SS
EM_RAS
EM_RW
SPI0_ENA
/I2C1_
SDA
SPI0_CLK
/I2C0_
SCL
SCL
DV
DD
V
DD
SS
15
16
19
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