Texas Instruments TMS320C6722 User Manual page 61

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31
7
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-13. CFGHPIAMSB Register Bit Field Description (0x4000 000C)
BIT NO. NAME
31:8 Reserved
7:0 HPIAMSB
31
7
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-14. CFGHPIAUMB Register Bit Field Description (0x4000 0010)
BIT NO. NAME
31:8 Reserved
7:0 HPIAUMB
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Figure 4-19. CFGHPIAMSB Register Bit Layout (0x4000 000C)
RESET READ
VALUE WRITE
N/A N/A Reads are indeterminate. Only 0s should be written to these bits.
0 R/W UHPI most significant byte of DSP address to access in Non-Multiplexed mode and
in Multiplexed Address and Data mode when PAGEM = 1. Sets bits [31:24] of the
DSP internal address as accessed through UHPI.
Figure 4-20. CFGHPIAUMB Register Bit Layout (0x4000 0010)
RESET READ
VALUE WRITE
N/A N/A Reads are indeterminate. Only 0s should be written to these bits.
0 R/W UHPI upper middle byte of DSP address to access in Non-Multiplexed mode and in
Multiplexed Address and Data mode when PAGEM = 1. Sets bits [23:16] of the DSP
internal address as accessed through UHPI.
TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
Reserved
HPIAMSB
R/W, 0
DESCRIPTION
Reserved
HPIAUMB
R/W, 0
DESCRIPTION
Peripheral and Electrical Specifications
SPRS268E – MAY 2005 – REVISED JANUARY 2007
8
0
8
0
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