Texas Instruments TMS320C6722 User Manual page 17

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Figure 2-6 shows the bit layout of the CFGPIN0 register and
31
7 6
PINCAP7 PINCAP6
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-10. CFGPIN0 Register Bit Field Description (0x4000 0000)
BIT NO. NAME
31:8 Reserved
7 PINCAP7
6 PINCAP6
5 PINCAP5
4 PINCAP4
3 PINCAP3
2 PINCAP2
1 PINCAP1
0 PINCAP0
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Reserved
5 4
PINCAP5 PINCAP4
Figure 2-6. CFGPIN0 Register Bit Layout (0x4000 0000)
Reads are indeterminate. Only 0s should be written to these bits.
SPI0_SOMI/I2C0_SDA pin state captured on rising edge of RESET pin.
SPI0_SIMO pin state captured on rising edge of RESET pin.
SPI0_CLK/I2C0_SCL pin state captured on rising edge of RESET pin.
SPI0_SCS/I2C1_SCL pin state captured on rising edge of RESET pin.
SPI0_ENA/I2C1_SDA pin state captured on rising edge of RESET pin.
AXR0[8]/AXR1[5]/SPI1_SOMI pin state captured on rising edge of RESET pin.
AXR0[9]/AXR1[4]/SPI1_SIMO pin state captured on rising edge of RESET pin.
AXR0[7]/SPI1_CLK pin state captured on rising edge of RESET pin.
TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
Table 2-10 contains a description of the bits.
3 2
PINCAP3 PINCAP2
DESCRIPTION
8
1 0
PINCAP1 PINCAP0
Device Overview 17