Texas Instruments TMS320C6722 User Manual page 50

TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
Table 4-7. EMIF Asynchronous Interface Timing Requirements
NO.
28 t
su(EM_DV-EM_CLKH)A
29 t
h(EM_CLKH-EM_DIV)A
30 t
su(EM_CLKH-EM_WAITV)A
31 t
h(EM_CLKH-EM_WAITIV)A
33 t
w(EM_WAIT)A
34 t
d(EM_WAITD-HOLD)A
35 t
su(EM_WAITA-HOLD)A
(1) E = SYSCLK3 (EM_CLK) period.
(2) These parameters apply to memories selected by EM_CS[2] in both normal and NAND modes.
(3) These parameters specify the number of EM_CLK cycles of latency between EM_WAIT being sampled at the device pin and the EMIF
entering the HOLD phase. However, the asynchronous setup (parameter 30) and hold time (parameter 31) around each EM_CLK edge
must also be met in order to ensure the EM_WAIT signal is correctly sampled.
(4) In Figure 4-13, it appears that there are more than 4 EM_CLK cycles encompassed by parameter 35. However, EM_CLK cycles that are
part of the extended wait period should not be counted; the 4 EM_CLK requirement is to the start of where the HOLD phase would
begin if there were no extended wait cycles.
Table 4-8. EMIF Asynchronous Interface Switching Characteristics
NO.
1 t
c(EM_CLK)
2 t
w(EM_CLK)
17 t
dis(EM_CLKH-EM_DHZ)S
18 t
ena(EM_CLKH-EM_DLZ)S
21 t
d(EM_CLKH-EM_CS2V)A
22 t
d(EM_CLKH-EM_WE_DQMV)A
23 t
d(EM_CLKH-EM_AV)A
24 t
d(EM_CLKH-EM_DV)A
25 t
d(EM_CLKH-EM_OEV)A
26 t
d(EM_CLKH-EM_RW)A
27 t
dis(EM_CLKH-EM_DDIS)A
32 t
d(EM_CLKH-EM_WE)A
(1) These parameters apply to memories selected by EM_CS[2] in both normal and NAND modes.
50 Peripheral and Electrical Specifications
Input setup time, read data valid on EM_D[31:0] before EM_CLK
rising
Input hold time, read data valid on EM_D[31:0] after EM_CLK rising
Setup time, EM_WAIT valid before EM_CLK rising edge
Hold time, EM_WAIT valid after EM_CLK rising edge
Pulse width of EM_WAIT assertion and deassertion
Delay from EM_WAIT sampled deasserted on EM_CLK rising to
beginning of HOLD phase
Setup before end of STROBE phase (if no extended wait states are
inserted) by which EM_WAIT must be sampled asserted on
EM_CLK rising in order to add extended wait states.
PARAMETER
Cycle time, EMIF clock EM_CLK
Pulse width, high or low, EMIF clock EM_CLK
Delay time, EM_CLK rising to EM_D[31:0] 3-stated
Output hold time, EM_CLK rising to EM_D[31:0] driving
Delay time, from EM_CLK rising edge to EM_CS[2] valid
Delay time, EM_CLK rising to EM_WE_DQM[3:0] valid
Delay time, EM_CLK rising to EM_A[12:0] and EM_BA[1:0] valid
Delay time, EM_CLK rising to EM_D[31:0] valid
Delay time, EM_CLK rising to EM_OE valid
Delay time, EM_CLK rising to EM_RW valid
Delay time, EM_CLK rising to EM_D[31:0] 3-stated
Delay time, EM_CLK rising to EM_WE valid
(1) (2)
MIN
5
2
5
0
2E + 5
(3)
4E
(4)
(1)
MIN
10
3
1.15
0
0
0
0
0
0
0
0
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MAX UNIT
ns
ns
ns
ns
ns
(3)
4E ns
ns
MAX UNIT
ns
ns
7.7 ns
ns
8 ns
8 ns
8 ns
8 ns
8 ns
8 ns
8 ns
8 ns