Texas Instruments TMS320C6722 User Manual page 14

TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
Figure 2-5 shows the bit layout of the device-level bridge control register (CFGBRIDGE) and
contains a description of the bits.
31
15
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-7. CFGBRIDGE Register Bit Field Description (0x4000 0024)
BIT NO. NAME
31:1 Reserved
0 CSPRST
The CSPRST bit must be asserted after any change to the PLL that affects SYSCLK1
and SYSCLK2 and must be released before any accesses to the CSP bridge occur
from either the dMAX or the UHPI.
14 Device Overview
Reserved
Figure 2-5. CFGBRIDGE Register Bit Layout (0x4000 0024)
RESET VALUE READ WRITE
N/A N/A
1 R/W
Reserved
Reads are indeterminate. Only 0s should be written to these bits.
Resets the CSP Bridge (BR2 in
1 = Bridge Reset Asserted
0 = Bridge Reset Released
CAUTION
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1
CSPRST
DESCRIPTION
Figure 2-4).
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Table 2-7
16
0
R/W, 1