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PARAMETER
1
PLLRST = 1 assertion time during initialization
2
Lock time before setting PLLEN = 1. After changing D0, PLLM, or
input clock.
3
PLL input frequency (PLLREF after D0
4
PLL multiplier values (PLLM)
5
PLL output frequency (PLLOUT before dividers D1, D2, D3)
6
SYSCLK1 frequency (set by PLLM and dividers D0, D1)
7
SYSCLK2 frequency (set by PLLM and dividers D0, D2)
8
SYSCLK3 frequency (set by PLLM and dividers D0, D3)
(1) Some values for the D0 divider produce results outside of this range and should not be selected.
(2) In general, selecting the PLL output clock rate closest to the maximum frequency will decrease clock jitter.
SYSCLK1, SYSCLK2, SYSCLK3 must be configured as aligned by setting ALNCTL[2:0]
to '1'; and the PLLCMD.GOSET bit must be written every time the dividers D1, D2, and
D3 are changed in order to make sure the change takes effect and preserves
alignment.
When changing the PLL parameters which affect the SYSCLK1, SYSCLK2, SYSCLK3
dividers, the bridge BR2 in
Table
2-7.
The PLL is an analog circuit and is sensitive to power supply noise. Therefore it has a dedicated 3.3-V
power pin (PLLHV) that should be connected to DV
illustrated in
Figure
BOARD
DV
(3.3 V)
DD
Place Filter and Capacitors as Close
to DSP as Possible
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Table 4-40. Allowed PLL Operating Conditions
(1)
)
Figure 2-4
4-44.
EMI Filter: TDK ACF451832−333, −223, −153, or −103,
Panasonic EXCCET103U, or Equivalent
Figure 4-44. PLL Power Supply Filter
TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
DEFAULT VALUE
N/A
N/A
x13
(2)
N/A
PLLOUT/1
PLLOUT/2
PLLOUT/3
CAUTION
CAUTION
must be reset by the CFGBRIDGE register. See
at the board level through an external filter, as
DD
+
10 mF
EMI
Filter
Peripheral and Electrical Specifications
SPRS268E – MAY 2005 – REVISED JANUARY 2007
ALLOWED SETTING OR RANGE
MIN
125 ns
187.5 µs
12 MHz
x4
140 MHz
Device Frequency
Specification
/2, /3, or /4 of SYSCLK1
EMIF Frequency
Specification
PLLHV
0.1 mF
MAX
50 MHz
x25
600 MHz
103
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