Table of Contents
Advertisement
TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
2.8 Boot Modes
The C672x DSP supports only one hardware bootmode option, this is to boot from the internal ROM
starting at address 0x0000 0000. Other bootmode options are implemented by a software bootloader
stored in ROM. The software bootloader uses the CFGPIN0 and CFGPIN1 registers, which capture the
state of various device pins at reset, to determine which mode to enter. Note that in practice, only a few
pins are used by the software.
Only an externally applied RESET causes the CFGPIN0 and CFGPIN1 registers to
recapture their associated pin values. Neither an emulator reset nor a RTI reset
causes these registers to update.
The ROM bootmodes include:
Parallel Flash on EM_CS[2]
SPI0 or I2C1 master mode from serial EEPROM
SPI0 or I2C1 slave mode from external MCU
UHPI from an external MCU
Table 2-9
describes the required boot pin settings at device reset for each bootmode.
BOOT MODE
UHPI
Parallel Flash
SPI0 Master
SPI0 Slave
I2C1 Master
I2C1 Slave
(1) When UHPI_HCS is 0, the state of the SPI0_SOMI, SPI0_SIMO, and SPI0_CLK pins is copied into the specified bits in the CFGHPI
register described in
Table
Refer to the C9230C100 TMS320C672x Floating-Point Digital Signal Processor ROM Data Manual
(literature number SPRS277) for details on supported bootmodes and their implementation.
16
Device Overview
Table 2-9. Required Boot Pin Settings at Device Reset
UHPI_HCS
0
1
1
1
1
1
4-12.
CAUTION
SPI0_SOMI
SPI0_SIMO
(1)
BYTEAD
FULL
0
0
0
1
1
www.ti.com
SPI0_CLK
(1)
(1)
NMUX
1
0
0
1
1
1
0
1
1
1
Submit Documentation Feedback
Advertisement
Table of Contents
