Texas Instruments TMS320C6722 User Manual page 84

TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
Table 4-26. General Timing Requirements for SPIx Slave Modes
NO.
9 t Cycle Time, SPIx_CLK, All Slave Modes
c(SPC)S
10 t Pulse Width High, SPIx_CLK, All Slave Modes
w(SPCH)S
11 t Pulse Width Low, SPIx_CLK, All Slave Modes
w(SPCL)S
Setup time, transmit data
written to SPI and output
12 t onto SPIx_SOMI pin before
su(SOMI_SPC)S
initial clock edge from
master.
Delay, subsequent bits
13 t valid on SPIx_SOMI after
d(SPC_SOMI)S
transmit edge of SPIx_CLK
Output hold time,
SPIx_SOMI valid after
14 t
oh(SPC_SOMI)S
receive edge of SPIxCLK,
except for final bit
Input Setup Time,
15 t SPIx_SIMO valid before
su(SIMO_SPC)S
receive edge of SPIx_CLK
Input Hold Time,
16 t SPIx_SIMO valid after
ih(SPC_SIMO)S
receive edge of SPIx_CLK
(1) P = SYSCLK2 period
(2) First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPIx_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPIx_SIMO.
(3) Measured from the termination of the write of new data to the SPI module, as evidenced by new output data appearing on the
SPIx_SOMI pin. In analyzing throughput requirements, additional internal bus cycles must be accounted for to allow data to be written to
the SPI module by either the DSP CPU or the dMAX.
(4) The final data bit will be held on the SPIx_SOMI pin until the SPIDAT0 or SPIDAT1 register is written with new data.
84 Peripheral and Electrical Specifications
Polarity = 0, Phase = 0,
to SPIx_CLK rising
Polarity = 0, Phase = 1,
to SPIx_CLK rising
Polarity = 1, Phase = 0,
to SPIx_CLK falling
(2) (3)
Polarity = 1, Phase = 1,
to SPIx_CLK falling
Polarity = 0, Phase = 0,
from SPIx_CLK rising
Polarity = 0, Phase = 1,
from SPIx_CLK falling
Polarity = 1, Phase = 0,
from SPIx_CLK falling
Polarity = 1, Phase = 1,
from SPIx_CLK rising
Polarity = 0, Phase = 0,
from SPIx_CLK falling
Polarity = 0, Phase = 1,
from SPIx_CLK rising
Polarity = 1, Phase = 0,
(4)
from SPIx_CLK rising
Polarity = 1, Phase = 1,
from SPIx_CLK falling
Polarity = 0, Phase = 0,
to SPIx_CLK falling
Polarity = 0, Phase = 1,
to SPIx_CLK rising
Polarity = 1, Phase = 0,
to SPIx_CLK rising
Polarity = 1, Phase = 1,
to SPIx_CLK falling
Polarity = 0, Phase = 0,
from SPIx_CLK falling
Polarity = 0, Phase = 1,
from SPIx_CLK rising
Polarity = 1, Phase = 0,
from SPIx_CLK rising
Polarity = 1, Phase = 1,
from SPIx_CLK falling
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(1)
MIN
greater of 8P or
100 ns
greater of 4P or
45 ns
greater of 4P or
45 ns
2P
2P
2P
2P
2P + 15
2P + 15
2P + 15
2P + 15
0.5t – 10
c(SPC)S
0.5t – 10
c(SPC)S
0.5t – 10
c(SPC)S
0.5t – 10
c(SPC)S
0.5P + 15
0.5P + 15
0.5P + 15
0.5P + 15
0.5P + 5
0.5P + 5
0.5P + 5
0.5P + 5
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MAX UNIT
256P ns
ns
ns
ns
ns
ns
ns
ns