Terminal Functions - Texas Instruments TMS320C6722 User Manual

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2.9.2 Terminal Functions

Table 2-12, the Terminal Functions table, identifies the external signal names, the associated pin/ball
numbers along with the mechanical package designator, the pin type (I, O, IO, OZ, or PWR), whether the
pin/ball has any internal pullup/pulldown resistors, whether the pin/ball is configurable as an IO in GPIO
mode, and a functional pin description.
SIGNAL NAME
EM_A[0]
EM_A[1]
EM_A[2]
EM_A[3]
EM_A[4]
EM_A[5]
EM_A[6]
EM_A[7]
EM_A[8]
EM_A[9]
EM_A[10]
EM_A[11]
EM_A[12]
EM_BA[0]
EM_BA[1]
EM_CS[0]
EM_CS[2]
EM_CAS
EM_RAS
EM_WE
EM_CKE
EM_CLK
EM_WE_DQM[0]
EM_WE_DQM[1]
EM_WE_DQM[2]
EM_WE_DQM[3]
EM_OE
EM_RW
EM_WAIT
(1) TYPE column refers to pin direction in functional mode. If a pin has more than one function with different directions, the functions are
separated with a slash (/).
(2) PULL column:
IPD = Internal Pulldown resistor
IPU = Internal Pullup resistor
(3) If the GPIO column is 'Y', then in GPIO mode, the pin is configurable as an IO unless otherwise marked.
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Table 2-12. Terminal Functions
GDH/
(1)
RFP TYPE PULL
ZDH
External Memory Interface (EMIF) Address and Control
91 J16 O
89 J15 O
88 K15 O
86 L16 O
84 L15 O
83 M16 O
80 M15 O
79 N16 O
76 N15 O
75 P16 O
93 H15 O
74 P15 O
- P12 O
96 G15 O
94 H16 O
97 F15 O
100 E15 O
37 R3 O
98 F16 O
38 T3 O
71 T14 O
70 R14 O
39 R4 O
67 T13 O
- P13 O
- R15 O
104 D15 O
102 E16 O
- D14 I
TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
(2) (3)
GPIO
- N
- N
- N
- N
- N
- N
- N EMIF Address Bus
- N
- N
- N
- N
- N
IPD N
- N
SDRAM Bank Address and Asynchronous Memory
Low-Order Address
- N
- N SDRAM Chip Select
- N Asynchronous Memory Chip Select
- N SDRAM Column Address Strobe
- N SDRAM Row Address Strobe
- N SDRAM/Asynchronous Write Enable
- N SDRAM Clock Enable
- N EMIF Output Clock
- N Write Enable or Byte Enable for EM_D[7:0]
- N Write Enable or Byte Enable for EM_D[15:8]
IPU N Write Enable or Byte Enable for EM_D[23:16]
IPU N Write Enable or Byte Enable for EM_D[31:24]
- N SDRAM/Asynchronous Output Enable
- N Asynchronous Memory Read/not Write
Asynchronous Wait Input (Programmable Polarity) or
IPU N
Interrupt (NAND)
SPRS268E – MAY 2005 – REVISED JANUARY 2007
DESCRIPTION
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