Texas Instruments TMS320C6722 User Manual page 83

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4.14.3 SPI Electrical Data/Timing
4.14.3.1 Serial Peripheral Interface (SPI) Timing
Table 4-25 through
through Figure 4-36).
Table 4-25. General Timing Requirements for SPIx Master Modes
NO.
1 t Cycle Time, SPIx_CLK, All Master Modes
c(SPC)M
2 t Pulse Width High, SPIx_CLK, All Master Modes
w(SPCH)M
3 t Pulse Width Low, SPIx_CLK, All Master Modes
w(SPCL)M
Delay, initial data bit valid
4 t on SPIx_SIMO to initial
d(SIMO_SPC)M
edge on SPIx_CLK
Delay, subsequent bits
5 t valid on SPIx_SIMO after
d(SPC_SIMO)M
transmit edge of SPIx_CLK
Output hold time,
SPIx_SIMO valid after
6 t
oh(SPC_SIMO)M
receive edge of SPIxCLK,
except for final bit
Input Setup Time,
7 t SPIx_SOMI valid before
su(SOMI_SPC)M
receive edge of SPIx_CLK
Input Hold Time,
8 t SPIx_SOMI valid after
ih(SPC_SOMI)M
receive edge of SPIx_CLK
(1) P = SYSCLK2 period
(2) First bit may be MSB or LSB depending upon SPI configuration. MO(0) refers to first bit and MO(n) refers to last bit output on
SPIx_SIMO. MI(0) refers to the first bit input and MI(n) refers to the last bit input on SPIx_SOMI.
(3) The final data bit will be held on the SPIx_SIMO pin until the SPIDAT0 or SPIDAT1 register is written with new data.
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Table 4-32 assume testing over recommended operating conditions (see
Polarity = 0, Phase = 0,
to SPIx_CLK rising
Polarity = 0, Phase = 1,
to SPIx_CLK rising
Polarity = 1, Phase = 0,
(2)
to SPIx_CLK falling
Polarity = 1, Phase = 1,
to SPIx_CLK falling
Polarity = 0, Phase = 0,
from SPIx_CLK rising
Polarity = 0, Phase = 1,
from SPIx_CLK falling
Polarity = 1, Phase = 0,
from SPIx_CLK falling
Polarity = 1, Phase = 1,
from SPIx_CLK rising
Polarity = 0, Phase = 0,
from SPIx_CLK falling
Polarity = 0, Phase = 1,
from SPIx_CLK rising
Polarity = 1, Phase = 0,
(3)
from SPIx_CLK rising
Polarity = 1, Phase = 1,
from SPIx_CLK falling
Polarity = 0, Phase = 0,
to SPIx_CLK falling
Polarity = 0, Phase = 1,
to SPIx_CLK rising
Polarity = 1, Phase = 0,
to SPIx_CLK rising
Polarity = 1, Phase = 1,
to SPIx_CLK falling
Polarity = 0, Phase = 0,
from SPIx_CLK falling
Polarity = 0, Phase = 1,
from SPIx_CLK rising
Polarity = 1, Phase = 0,
from SPIx_CLK rising
Polarity = 1, Phase = 1,
from SPIx_CLK falling
TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
greater of 8P or
100 ns
greater of 4P or 45 ns
greater of 4P or 45 ns
0.5t
c(SPC)M
0.5t
c(SPC)M
0.5t
c(SPC)M
0.5t
c(SPC)M
0.5t
c(SPC)M
0.5t
c(SPC)M
0.5P + 15
0.5P + 15
0.5P + 15
0.5P + 15
0.5P + 5
0.5P + 5
0.5P + 5
0.5P + 5
Peripheral and Electrical Specifications
Figure 4-33
(1)
MIN MAX UNIT
256P ns
ns
ns
4P
+ 4P
ns
4P
+ 4P
15
15
ns
15
15
– 10
– 10
ns
– 10
– 10
ns
ns
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