Texas Instruments TMS320C6722 User Manual page 18

TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
Figure 2-7 shows the bit layout of the CFGPIN1 register and
31
7 6
PINCAP15 PINCAP14
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 2-11. CFGPIN1 Register Bit Field Description (0x4000 0004)
BIT NO. NAME
31:8 Reserved
7 PINCAP15
6 PINCAP14
5 PINCAP13
4 PINCAP12
3 PINCAP11
2 PINCAP10
1 PINCAP9
0 PINCAP8
18 Device Overview
Reserved
5 4
PINCAP13 PINCAP12
Figure 2-7. CFGPIN1 Register Bit Layout (0x4000 0004)
Reads are indeterminate. Only 0s should be written to these bits.
AXR0[5]/SPI1_SCS pin state captured on rising edge of RESET pin.
AXR0[6]/SPI1_ENA pin state captured on rising edge of RESET pin.
UHPI_HCS pin state captured on rising edge of RESET pin.
UHPI_HD[0] pin state captured on rising edge of RESET pin.
EM_D[16]/UHPI_HA[0] pin state captured on rising edge of RESET pin.
AFSX0 pin state captured on rising edge of RESET pin.
AFSR0 pin state captured on rising edge of RESET pin.
AXR0[0] pin state captured on rising edge of RESET pin.
Table 2-11 contains a description of the bits.
3 2
PINCAP11 PINCAP10
DESCRIPTION
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8
1 0
PINCAP9 PINCAP8
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