High-Performance Crossbar Switch - Texas Instruments TMS320C6722 User Manual

TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007

2.6 High-Performance Crossbar Switch

The C672x DSP includes a high-performance crossbar switch that acts as a central hub between bus
masters and targets.
ROM RAM CPU
Memory Controller
Data CPU
Master Slave
Port Port
(DMP) (CSP)
M1 T1
BR1 BR2
SYSCLK1 SYSCLK1
SYSCLK2 SYSCLK2
Priority
1 2
UHPI Master Interface (External Host CPU)
Crossbar
External
Host MCU
As shown in Figure
M1
M2
M3
M4
M5
12 Device Overview
Figure 2-4 illustrates the connectivity of the crossbar switch.
Program
EMIF
Cache
T2
Program
Master
Port
(PMP) Priority
M2 2
BR3 BR4
SYSCLK3
SYSCLK1
3 1
dMAX MAX0 Unit Master Port − High Priority
dMAX MAX1 Unit Master Port − Second Priority
Memory Controller DMP − Data Read/Write by CPU
M5
UHPI
Universal Host-Port
Interface
Figure 2-4. Block Diagram of Crossbar Switch
2-4, there are five bus masters:
Memory controller DMP for CPU data accesses to peripherals and EMIF.
Memory controller PMP for program cache fills from the EMIF.
dMAX HiMAX master port for high-priority DMA accesses.
dMAX LoMAX master port for lower-priority DMA accesses.
UHPI master port for an external MCU to access on-chip and off-chip memories.
External
Memory
SDRAM/
Flash
1
SYSCLK3
SYSCLK2
Priority
2 3 4
M3
Config
MAX0
PLL RTI SPI0 SPI1
Peripheral Configuration Bus
T3
McASP0 McASP1
McASP DMA Bus
T4
Priority Priority
1 2 3 1
1 2
Priority
M4 T5
MAX1 Config
dMAX
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I2C0 I2C1
McASP2
2
3