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C6727
DSP EMIF
EM_WE_DQM[0]
EM_WE_DQM[1]
EM_WE_DQM[2]
EM_WE_DQM[3]
EM_D[31:16]/UHPI_HA[15:0]
RESET
RESET
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EM_CS[0]
EM_CAS
EM_RAS
EM_WE
EM_CLK
EM_CKE
EM_BA[1:0]
EM_A[12:0]
EM_D[15:0]
EM_CS[2]
EM_RW
EM_OE
EM_WAIT
GPIO
(5 Pins)
Any GPIO-capable pins which
can be pulled down at reset
can be used to control A[18:14]
for FLASH BOOTLOAD
Examples: AHCLKR0, SPI0_SCS/SCL1
Figure 4-6. C6727 DSP 32-Bit EMIF Example
TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
4M x 16 x 4 Bank
CE
CAS
RAS
WE
CLK
CKE
BA[1:0]
A[12:0]
LDQM
UDQM
DQ[15:0]
4M x 16 x 4 Bank
CE
CAS
RAS
WE
CLK
CKE
BA[1:0]
A[12:0]
LDQM
UDQM
DQ[15:0]
EM_BA[1]
A[0]
A[13:1]
DQ[15:0]
CE
WE
OE
RESET
A[18:14]
RY/BY
Peripheral and Electrical Specifications
SDRAM
SDRAM
FLASH
512K x 16
47
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