Texas Instruments TMS320C6722 User Manual page 70

TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007
4.13.1 McASP Peripheral Registers Description(s)
Table 4-18 is a list of the McASP registers. For more information about these registers, see the
TMS320C672x DSP Multichannel Audio Serial Port (McASP) Reference Guide (literature number
SPRU878).
Table 4-18. McASP Registers Accessed Through Peripheral Configuration Bus
McASP0 McASP1
BYTE BYTE
ADDRESS ADDRESS
0x4000 0018 0x4000 001C
0x4400 0000 0x4500 0000
0x4400 0004 0x4500 0004
0x4400 0010 0x4500 0010
0x4400 0014 0x4500 0014
0x4400 0018 0x4500 0018
0x4400 001C 0x4500 001C
0x4400 0020 0x4500 0020
0x4400 0044 0x4500 0044
0x4400 0048 0x4500 0048
0x4400 004C 0x4500 004C
0x4400 0050 0x4500 0050
0x4400 0060 0x4500 0060
0x4400 0064 0x4500 0064
0x4400 0068 0x4500 0068
0x4400 006C 0x4500 006C
0x4400 0070 0x4500 0070
0x4400 0074 0x4500 0074
0x4400 0078 0x4500 0078
0x4400 007C 0x4500 007C
0x4400 0080 0x4500 0080
0x4400 0084 0x4500 0084
0x4400 0088 0x4500 0088
0x4400 008C 0x4500 008C
0x4400 00A0 0x4500 00A0
0x4400 00A4 0x4500 00A4
0x4400 00A8 0x4500 00A8
0x4400 00AC 0x4500 00AC
0x4400 00B0 0x4500 00B0
0x4400 00B4 0x4500 00B4
0x4400 00B8 0x4500 00B8
0x4400 00BC 0x4500 00BC
0x4400 00C0 0x4500 00C0
0x4400 00C4 0x4500 00C4
70 Peripheral and Electrical Specifications
McASP2
REGISTER
BYTE
NAME
ADDRESS
Device-Level Configuration Registers Controlling McASP
0x4000 0020 CFGMCASPx
McASP Internal Registers
0x4600 0000 PID
0x4600 0004 PWRDEMU
0x4600 0010 PFUNC
0x4600 0014 PDIR
0x4600 0018 PDOUT
0x4600 001C PDIN (reads)
PDSET (writes)
0x4600 0020 PDCLR
0x4600 0044 GBLCTL
0x4600 0048 AMUTE
0x4600 004C DLBCTL
0x4600 0050 DITCTL
0x4600 0060 RGBLCTL
0x4600 0064 RMASK
0x4600 0068 RFMT
0x4600 006C AFSRCTL
0x4600 0070 ACLKRCTL
0x4600 0074 AHCLKRCTL
0x4600 0078 RTDM
0x4600 007C RINTCTL
0x4600 0080 RSTAT
0x4600 0084 RSLOT
0x4600 0088 RCLKCHK
0x4600 008C REVTCTL
0x4600 00A0 XGBLCTL
0x4600 00A4 XMASK
0x4600 00A8 XFMT
0x4600 00AC AFSXCTL
0x4600 00B0 ACLKXCTL
0x4600 00B4 AHCLKXCTL
0x4600 00B8 XTDM
0x4600 00BC XINTCTL
0x4600 00C0 XSTAT
0x4600 00C4 XSLOT
DESCRIPTION
Selects the peripheral pin to be used as AMUTEINx
Peripheral identification register
Power down and emulation management register
Pin function register
Pin direction register
Pin data output register
Read returns: Pin data input register
Writes affect: Pin data set register
(alternate write address: PDOUT)
Pin data clear register (alternate write address: PDOUT)
Global control register
Audio mute control register
Digital loopback control register
DIT mode control register
Receiver global control register: Alias of GBLCTL, only
receive bits are affected - allows receiver to be reset
independently from transmitter
Receive format unit bit mask register
Receive bit stream format register
Receive frame sync control register
Receive clock control register
Receive high-frequency clock control register
Receive TDM time slot 0-31 register
Receiver interrupt control register
Receiver status register
Current receive TDM time slot register
Receive clock check control register
Receiver DMA event control register
Transmitter global control register. Alias of GBLCTL, only
transmit bits are affected - allows transmitter to be reset
independently from receiver
Transmit format unit bit mask register
Transmit bit stream format register
Transmit frame sync control register
Transmit clock control register
Transmit high-frequency clock control register
Transmit TDM time slot 0-31 register
Transmitter interrupt control register
Transmitter status register
Current transmit TDM time slot register
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