Data Clock Generation; Input Clock Source Mode: Clksm; Sample Rate Generator Data Bit Clock Rate: Clkgdv - Texas Instruments TMS320C6000 Reference Manual

4.3

Data Clock Generation

4.3.1

Input Clock Source Mode: CLKSM

4.3.2

Sample Rate Generator Data Bit Clock Rate: CLKGDV

SPRU580C
When the receive/transmit clock mode is set to 1 (CLK(R/X)M = 1), the data
clocks (CLK(R/X)) are driven by the internal sample rate generator output
clock, CLKG. You can select for the receiver and transmitter from a variety of
data bit clocks including:
The input clock to the sample rate generator, which can be either the
-
internal clock source or a dedicated external clock source (CLKS). The
C620x/C670x DSP uses the CPU clock as the internal clock source to the
sample rate generator. The C621x/C671x DSP uses the CPU/2 clock as
the internal clock source. The C64x DSP uses the CPU/4 clock as the
internal clock source to the sample rate generator.
The input clock source (internal clock source or external clock CLKS) to
-
the sample rate generator can be divided down by a programmable value
(CLKGDV) to drive CLKG.
Regardless of the source to the sample rate generator, the rising edge of
CLKSRG (see Figure 6) generates CLKG and FSG (see section 4.3.3).
The CLKSM bit in SRGR selects either the internal clock (CLKSM = 1) or the
external clock input (CLKSM = 0), CLKS, as the source for the sample rate
generator input clock. Any divide periods are divide-downs calculated by the
sample rate generator and are timed by this input clock selection.
The first divider stage generates the serial data bit clock from the input clock.
This divider stage uses a counter that is preloaded by CLKGDV and that
contains the divide ratio value. The output of this stage is the data bit clock that
is output on the sample rate generator output, CLKG, and that serves as the
input for the second and third divider stages.
CLKG has a frequency equal to 1/(CLKGDV + 1) of the sample rate generator
input clock. Thus, the sample rate generator input clock frequency is divided
by a value between 1 to 256. When CLKGDV is an odd value or equal to 0, the
CLKG duty cycle is 50%. Note that an odd CLKGDV value means an even
divide down of the source clock and an even CLKGDV value means an odd
divide down of the source clock. When CLKGDV is an even value (2p), the high
state duration is p + 1 cycles and the low state duration is p cycles. This is
illustrated in Example 1, Example 2, and Example 3.
Multichannel Buffered Serial Port (McBSP)
Clocks, Frames, and Data
23