Phase-Locked Loop (Pll) - Texas Instruments TMS320C6722 User Manual

TMS320C6727, TMS320C6726, TMS320C6722
Floating-Point Digital Signal Processors
SPRS268E – MAY 2005 – REVISED JANUARY 2007

4.18 Phase-Locked Loop (PLL)

4.18.1 PLL Device-Specific Information
The C672x DSP generates the high-frequency internal clocks it requires through an on-chip PLL.
The input to the PLL is either from the on-chip oscillator (OSCIN pin) or from an external clock on the
CLKIN pin. The PLL outputs four clocks that have programmable divider options.
the PLL Topology.
The PLL is disabled by default after a device reset. It must be configured by software according to the
allowable operating conditions listed in
PLLEN = 1.
Clock
Divider
Input
D0
from
(/1 to /32)
CLKIN or
OSCIN
102 Peripheral and Electrical Specifications
Table 4-40
PLLOUT
PLLREF
PLL
x4 to x25
Figure 4-43. PLL Topology
before enabling the DSP to run from the PLL by setting
PLLEN
(PLL_CSR[0])
1
Divider
D1
(/1 to /32)
0
Divider
D2
(/1 to /32)
Divider
D3
(/1 to /32)
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Figure 4-43 illustrates
SYSCLK1
CPU and Memory
SYSCLK2
Peripherals and dMAX
SYSCLK3
EMIF
AUXCLK
McASP0,1,2
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