Terminology - Intel I5-520E - DATASHEET ADDENDUM Datasheet

1.4

Terminology

BLT
CRT
DDR3
DP
DMA
DMI
DTS
ECC
eDP*
®
Intel DPST
Enhanced Intel
SpeedStep
Execute Disable Bit
EU
(G)MCH
GPU
ICH
IMC
®
Intel 64 Technology
®
Intel FDI
®
Intel TXT
®
Intel Virtualization
Technology
ITPM
IOV
LCD
LVDS
MCP
NCTF
PCH
PECI
® TM
Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel
Datasheet Addendum
12
Term
Block Level Transfer
Cathode Ray Tube
Third generation Double Data Rate SDRAM memory technology
DisplayPort*
Direct Memory Access
Direct Media Interface
Digital Thermal Sensor
Error Correction Code
Embedded DisplayPort*
®
Intel Display Power Saving Technology
Technology that provides power management capabilities to laptops.
®
Technology
The Execute Disable bit allows memory to be marked as executable or non-
executable, when combined with a supporting operating system. If code
attempts to run in non-executable memory the processor raises an error to the
operating system. This feature can prevent some classes of viruses or worms
that exploit buffer overrun vulnerabilities and can thus help improve the overall
security of the system. See the Intel® 64 and IA-32 Architectures Software
Developer's Manuals for more detailed information.
Execution Unit
Legacy component - Graphics Memory Controller Hub.
Graphics Processing Unit
The legacy I/O Controller Hub component that contains the main PCI interface,
LPC interface, USB2, Serial ATA, and other I/O functions. It communicates with
the legacy (G)MCH over a proprietary interconnect called DMI.
Integrated Memory Controller
64-bit memory extensions to the IA-32 architecture.
®
Intel Flexible Display Interface.
®
Intel Trusted Execution Technology
Processor virtualization which when used in conjunction with Virtual Machine
Monitor software enables multiple, robust independent software environments
inside a single platform.
Integrated Trusted Platform Module
I/O Virtualization
Liquid Crystal Display
Low Voltage Differential Signaling
A high speed, low power data transmission standard used for display connections
to LCD panels.
Multi-Chip Package
Non-Critical to Function: NCTF locations are typically redundant ground or non-
critical reserved, so the loss of the solder joint continuity at end of life conditions
will not affect the overall product functionality.
Platform Controller Hub. The new 2009 chipset with centralized platform
capabilities including the main I/O interfaces along with display connectivity,
audio features, power management, manageability, security and storage
features. The PCH may also be referred to using the code name Ibex Peak.
Platform Environment Control Interface
®
Celeron
Introduction and Features Summary
Description
®
Processor P4500, P4505 Series
April 2010
Document Number: 323178-002