Error Command Registers - Intel I5-520E - DATASHEET ADDENDUM Datasheet

Table 17.

Error Command Registers

Bit
15:12
11
10
9
8
7
6:2
1
0
® TM
Intel Core i7-620LE/UE, i7-610E, i5-520E and Intel
Datasheet Addendum
74
Access Default
Value
RO 000b
RW 0b
RO 0b
RW 0b
RW 0b
RW 0b
RO 00h
RW 0b
RW 0b
®
Celeron
Processor Configuration Registers
RST/
PWR
Core Reserved
Core SERR on Processor Thermal Sensor Event
(TSESERR):
1: The Processor generates a DMI SERR special
cycle when bit 11 of the ERRSTS is set. The
SERR must not be enabled at the same time as
the SMI for the same thermal sensor event.
0: Reporting of this condition via SERR
messaging is disabled.
Core Reserved
Core SERR on LOCK to non-DRAM Memory
(LCKERR):
1: The Processor will generate a DMI SERR
special cycle whenever a CPU lock cycle is
detected that does not hit DRAM.
0: Reporting of this condition via SERR
messaging is disabled
Core Reserved
Core
SERR on DRAM Throttle Condition (ERR):
0 = Reporting of this condition via SERR
messaging is disabled.
1 = The memory controller generates a DMI
SERR special cycle when a DRAM Read or Write
Throttle condition occurs.
Core
Reserved
Core SERR Multiple-Bit DRAM ECC Error
(DMERR):
1: The Processor generates an SERR message
over DMI when it detects a multiple-bit error
reported by the DRAM controller.
0: Reporting of this condition via SERR
messaging is disabled.
For systems not supporting ECC this bit must
be disabled.
Core SERR on Single-bit ECC Error (DSERR):
1: The Processor generates an SERR special
cycle over DMI when the DRAM controller
detects a single bit error.
0: Reporting of this condition via SERR
messaging is disabled.
For systems that do not support ECC this bit
must be disabled.
®
Processor P4500, P4505 Series
Description
April 2010
Document Number: 323178-002